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2011 International Reliability Physics Symposium最新文献

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Negative bias temperature instability “multi-mode” compact model based on threshold voltage and mobility degradation 基于阈值电压和迁移率退化的负偏置温度不稳定性“多模”紧凑模型
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784451
D. Varghese, R. Higgins, S. Dunn, A. Krishnan, V. Reddy, S. Krishnan
{"title":"Negative bias temperature instability “multi-mode” compact model based on threshold voltage and mobility degradation","authors":"D. Varghese, R. Higgins, S. Dunn, A. Krishnan, V. Reddy, S. Krishnan","doi":"10.1109/IRPS.2011.5784451","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784451","url":null,"abstract":"In this paper we have developed a model to obtain drain current (ID) degradation at all transistor operating modes (linear, saturation and sub-threshold) during NBTI stress based on threshold voltage (VT) and mobility (µ) degradation. This model provides a compact way to comprehend NBTI induced drain current degradation for transistors subject to multiple operating modes (e.g., dynamic voltage scaling, active/standby modes).","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117124099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel and low-cost method to detect delay variation by dynamic thermal laser stimulation 动态热激光刺激检测延迟变化的一种新颖、低成本的方法
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784574
Chunlei Wu, M. Motohiko, Winter Wang, G. Song, Jinglong Li, J. Yu, Li Tian, Miao Wu
{"title":"A novel and low-cost method to detect delay variation by dynamic thermal laser stimulation","authors":"Chunlei Wu, M. Motohiko, Winter Wang, G. Song, Jinglong Li, J. Yu, Li Tian, Miao Wu","doi":"10.1109/IRPS.2011.5784574","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784574","url":null,"abstract":"Delay variation can be very difficult to localize in function failure analysis. In this paper we combine Delay Variation Mapping (DVM) and Soft Defect Localization (SDL) to develop a novel and low-cost method that can detect delay variation effectively. It just uses Static Thermal Laser Stimulation (S-TLS), Oscilloscope and Function Generator to compose a dynamic thermal laser stimulation (D-TLS) system. The methodology, system configuration and experimental results of this method are presented.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115743031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Impact of scaling on the performance and reliability degradation of metal-contacts in NEMS devices 缩放对NEMS器件中金属触点性能和可靠性退化的影响
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784489
H. Dadgour, M. Hussain, A. Cassell, Navab Singh, K. Banerjee
{"title":"Impact of scaling on the performance and reliability degradation of metal-contacts in NEMS devices","authors":"H. Dadgour, M. Hussain, A. Cassell, Navab Singh, K. Banerjee","doi":"10.1109/IRPS.2011.5784489","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784489","url":null,"abstract":"Nano-electro-mechanical switches (NEMS) offer new possibilities for the design of ultra energy-efficient systems; however, thus far, all the fabricated NEMS devices require high supply voltages that limit their applicability for logic designs. Therefore, research is being conducted to lower the operating voltages by scaling down the physical dimensions of these devices. However, the impact of device scaling on the electrical and mechanical properties of metal contacts in NEMS devices has not been thoroughly investigated in the literature. Such a study is essential because metal contacts play a critical role in determining the overall performance and reliability of NEMS. Therefore, the comprehensive analytical study presented in this paper highlights the performance and reliability degradations of such metal contacts caused by scaling. The proposed modeling environment accurately takes into account the impact of roughness of contact surfaces, elastic/plastic deformation of contacting asperities, and various inter-molecular forces between mating surfaces (such as Van der Waals and capillary forces). The modeling results are validated and calibrated using available measurement data. This scaling analysis indicates that the key contact properties of gold contacts (resistance, stiction and wear-out) deteriorate “exponentially” with scaling. Simulation results demonstrate that reliable (stiction-free) operation of very small contact areas (≈ 6nm × 6nm) will be a daunting task due to the existence of strong surface forces. Hence, contact degradation is identified as a major problem to the scaling of NEMS transistors.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132422364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Electromigration induced void kinetics in Cu interconnects for advanced CMOS nodes 先进CMOS节点铜互连中电迁移诱导空洞动力学
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784491
L. Arnaud, P. Lamontagne, R. Galand, E. Petitprez, D. Ney, P. Waltz
{"title":"Electromigration induced void kinetics in Cu interconnects for advanced CMOS nodes","authors":"L. Arnaud, P. Lamontagne, R. Galand, E. Petitprez, D. Ney, P. Waltz","doi":"10.1109/IRPS.2011.5784491","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784491","url":null,"abstract":"Time evolution of resistance during EM tests is extensively analyzed for various Cu interconnect structures and processes from the 40 nm node technology. Resistance evolution is used to model void nucleation and growth kinetics. We show that adding Al or other impurities in the line is effective to increase electromigration lifetime. This lifetime increase is due, as expected, to Cu drift velocity decrease but also to an increase of the time to void formation. TEM picture shows that Al precipitates are formed at grain boundaries and are most likely responsible for the occurrence of an incubation time Resistance saturation is observed for short lines thanks to Blech effect. A resistance model is developed to characterize short length effect in 40 nm node. The model is also used to explain EM lifetime improvement thanks to a pre-stress condition where compressive stress is added at cathode end of long line structures.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131256087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Stability improvement of a-ZIO TFT circuits using low temperature anneal 低温退火提高a-ZIO TFT电路的稳定性
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784601
A. Dey, D. Allee
{"title":"Stability improvement of a-ZIO TFT circuits using low temperature anneal","authors":"A. Dey, D. Allee","doi":"10.1109/IRPS.2011.5784601","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784601","url":null,"abstract":"Long duration of low temperature thermal anneals show performance and stability enhancement for low-temperature fabricated amorphous zinc-indium-oxide (a-ZIO) thin-film-transistors (TFTs). The turn-on voltage (Von) of 50 hour annealed TFTs shifts by 1.5 V for a positive gate bias stress period of 104 s when compared to a 2.2 V shift for the unannealed TFTs. The performance and stability improvements are attributed to a reduction of the interface trap density and removing of defects states in the band-gap of the a-ZIO.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127238581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Time evolution of electrical degradation under high-voltage stress in GaN high electron mobility transistors GaN高电子迁移率晶体管在高压应力下电退化的时间演化
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784511
J. Joh, J. D. del Alamo
{"title":"Time evolution of electrical degradation under high-voltage stress in GaN high electron mobility transistors","authors":"J. Joh, J. D. del Alamo","doi":"10.1109/IRPS.2011.5784511","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784511","url":null,"abstract":"In this work, we investigate the time evolution of electrical degradation of GaN high electron mobility transistors under high voltage stress in the OFF state. We found that the gate current starts to degrade first, followed by degradation in current collapse and eventually permanent degradation in ID. We also found that the time evolution of gate current degradation is unaffected by temperature, while drain current degradation is thermally accelerated.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126787459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A new ESD model induced yield loss during chip-on-film package process and it's failure mechanism 提出了片上封装过程中产生良率损失的新型静电放电模型及其失效机理
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784558
Jian-Hsing Lee, J. Shih, Yu-Hui Huang, C. Lin, D. Su, Kenneth Wu
{"title":"A new ESD model induced yield loss during chip-on-film package process and it's failure mechanism","authors":"Jian-Hsing Lee, J. Shih, Yu-Hui Huang, C. Lin, D. Su, Kenneth Wu","doi":"10.1109/IRPS.2011.5784558","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784558","url":null,"abstract":"A new model of electrostatic discharge (ESD) event is found in ICs during chip-on-film (COF) package. The behavior of this new kind of ESD is different from the human-body mode (HBM), machine model (MM) and charge device model (CDM) model. We call it the charge tape model (CTM). It often damages the gate oxides of the input circuit and output circuit in IC to result in the yield loss. The mechanism of COF package induced yield loss has been identified. Two factors dominate the yield loss. One is the ESD generation on the tape surface during COF tape reeled out process. The other one is the required high temperature for the inner lead bonding, which lowers the breakdown voltage of the gate oxide. As a result, an IC might be damaged to induce the yield loss.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116845426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Atomistic approach to variability of bias-temperature instability in circuit simulations 电路模拟中偏温不稳定性变率的原子方法
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784604
B. Kaczer, S. Mahato, V. V. D. A. Camargo, M. Toledano-Luque, P. Roussel, T. Grasser, F. Catthoor, P. Dobrovolný, P. Zuber, G. Wirth, G. Groeseneken
{"title":"Atomistic approach to variability of bias-temperature instability in circuit simulations","authors":"B. Kaczer, S. Mahato, V. V. D. A. Camargo, M. Toledano-Luque, P. Roussel, T. Grasser, F. Catthoor, P. Dobrovolný, P. Zuber, G. Wirth, G. Groeseneken","doi":"10.1109/IRPS.2011.5784604","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784604","url":null,"abstract":"A blueprint for an atomistic approach to introducing time-dependent variability into a circuit simulator in a realistic manner is demonstrated. The approach is based on previously proven physics of stochastic properties of individual gate oxide defects and their impact on FET operation. The proposed framework is capable of following defects with widely distributed time scales (from fast to quasi-permanent), thus seamlessly integrating random telegraph noise (RTN) effects with bias temperature instability (BTI). The use of industry-standard circuit simulation tools allows for studying realistic workloads and the interplay of degradation of multiple FETs.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116951000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 138
The impact of new technology on soft error rates 新技术对软错误率的影响
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784522
A. Dixit, A. Wood
{"title":"The impact of new technology on soft error rates","authors":"A. Dixit, A. Wood","doi":"10.1109/IRPS.2011.5784522","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784522","url":null,"abstract":"This paper presents the impact of new microprocessor technology on microprocessor soft error rate (SER). The results are based on Oracle's (formerly Sun Microsystems) neutron beam testing over the past several years. We describe how the tests were conducted and how the test results are used to influence microprocessor design. As microprocessor feature sizes decreased from 180nm to 65nm, memory error rates per bit decreased, but our data indicates a reversal of this trend at 40nm. Flop error rates still appear to be decreasing, even at a 28nm feature size We measure SER as a function of power supply voltage (Vdd) over a range of 1.2V down to 0.5V, and the data shows SER significantly increases as Vdd decreases. This result implies that dynamic voltage frequency scaling (DVFS), a commonly used microprocessor energy reduction technique, could cause a significant decrease in microprocessor reliability. The data also show that more energy-efficient transistors using back bias technique do not appear to significantly impact microprocessor reliability.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114665842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 303
Split-gate flash memory for automotive embedded applications 用于汽车嵌入式应用的分门快闪存储器
2011 International Reliability Physics Symposium Pub Date : 2011-04-10 DOI: 10.1109/IRPS.2011.5784547
Y.S. Chu, Y.H. Wang, C. Wang, Y. Lee, A. Kang, R. Ranjan, W. Chu, T. Ong, H. W. Chin, K. Wu
{"title":"Split-gate flash memory for automotive embedded applications","authors":"Y.S. Chu, Y.H. Wang, C. Wang, Y. Lee, A. Kang, R. Ranjan, W. Chu, T. Ong, H. W. Chin, K. Wu","doi":"10.1109/IRPS.2011.5784547","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784547","url":null,"abstract":"An embedded split-gate flash memory based on 65nm logic process technology has been developed. The design rules for split-gate flash macro's testability and reliability are discussed. An automotive grade flash memory with 100K endurance, 10 years, 125°C data retention, and 1-ppm requirement has been demonstrated with a comprehensive dielectric screen methodology. Both erase time push out and data retention dominant mechanisms are thoroughly studied with intrinsic lifetime and large sample certification. An automotive embedded split-gate flash solution in 65nm technology is ready for commercialization.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117350409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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