提出了片上封装过程中产生良率损失的新型静电放电模型及其失效机理

Jian-Hsing Lee, J. Shih, Yu-Hui Huang, C. Lin, D. Su, Kenneth Wu
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引用次数: 0

摘要

在片上封装过程中发现了一种新的静电放电(ESD)模型。这种新型静电放电的行为不同于人体模型(HBM)、机器模型(MM)和电荷器件模型(CDM)。我们称之为电荷带模型(CTM)。在集成电路中,输入电路和输出电路的栅极氧化物经常受到破坏,从而造成良率损失。确定了COF包封导致产量损失的机理。造成产量损失的主要因素有两个。一是在COF胶带卷出过程中,在胶带表面产生ESD。另一个是内引线键合所需的高温,这降低了栅极氧化物的击穿电压。因此,集成电路可能会损坏,从而导致良率损失。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A new ESD model induced yield loss during chip-on-film package process and it's failure mechanism
A new model of electrostatic discharge (ESD) event is found in ICs during chip-on-film (COF) package. The behavior of this new kind of ESD is different from the human-body mode (HBM), machine model (MM) and charge device model (CDM) model. We call it the charge tape model (CTM). It often damages the gate oxides of the input circuit and output circuit in IC to result in the yield loss. The mechanism of COF package induced yield loss has been identified. Two factors dominate the yield loss. One is the ESD generation on the tape surface during COF tape reeled out process. The other one is the required high temperature for the inner lead bonding, which lowers the breakdown voltage of the gate oxide. As a result, an IC might be damaged to induce the yield loss.
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