Jian-Hsing Lee, J. Shih, Yu-Hui Huang, C. Lin, D. Su, Kenneth Wu
{"title":"提出了片上封装过程中产生良率损失的新型静电放电模型及其失效机理","authors":"Jian-Hsing Lee, J. Shih, Yu-Hui Huang, C. Lin, D. Su, Kenneth Wu","doi":"10.1109/IRPS.2011.5784558","DOIUrl":null,"url":null,"abstract":"A new model of electrostatic discharge (ESD) event is found in ICs during chip-on-film (COF) package. The behavior of this new kind of ESD is different from the human-body mode (HBM), machine model (MM) and charge device model (CDM) model. We call it the charge tape model (CTM). It often damages the gate oxides of the input circuit and output circuit in IC to result in the yield loss. The mechanism of COF package induced yield loss has been identified. Two factors dominate the yield loss. One is the ESD generation on the tape surface during COF tape reeled out process. The other one is the required high temperature for the inner lead bonding, which lowers the breakdown voltage of the gate oxide. As a result, an IC might be damaged to induce the yield loss.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A new ESD model induced yield loss during chip-on-film package process and it's failure mechanism\",\"authors\":\"Jian-Hsing Lee, J. Shih, Yu-Hui Huang, C. Lin, D. Su, Kenneth Wu\",\"doi\":\"10.1109/IRPS.2011.5784558\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new model of electrostatic discharge (ESD) event is found in ICs during chip-on-film (COF) package. The behavior of this new kind of ESD is different from the human-body mode (HBM), machine model (MM) and charge device model (CDM) model. We call it the charge tape model (CTM). It often damages the gate oxides of the input circuit and output circuit in IC to result in the yield loss. The mechanism of COF package induced yield loss has been identified. Two factors dominate the yield loss. One is the ESD generation on the tape surface during COF tape reeled out process. The other one is the required high temperature for the inner lead bonding, which lowers the breakdown voltage of the gate oxide. As a result, an IC might be damaged to induce the yield loss.\",\"PeriodicalId\":242672,\"journal\":{\"name\":\"2011 International Reliability Physics Symposium\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRPS.2011.5784558\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2011.5784558","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new ESD model induced yield loss during chip-on-film package process and it's failure mechanism
A new model of electrostatic discharge (ESD) event is found in ICs during chip-on-film (COF) package. The behavior of this new kind of ESD is different from the human-body mode (HBM), machine model (MM) and charge device model (CDM) model. We call it the charge tape model (CTM). It often damages the gate oxides of the input circuit and output circuit in IC to result in the yield loss. The mechanism of COF package induced yield loss has been identified. Two factors dominate the yield loss. One is the ESD generation on the tape surface during COF tape reeled out process. The other one is the required high temperature for the inner lead bonding, which lowers the breakdown voltage of the gate oxide. As a result, an IC might be damaged to induce the yield loss.