Stability improvement of a-ZIO TFT circuits using low temperature anneal

Abstract

Long duration of low temperature thermal anneals show performance and stability enhancement for low-temperature fabricated amorphous zinc-indium-oxide (a-ZIO) thin-film-transistors (TFTs). The turn-on voltage (Von) of 50 hour annealed TFTs shifts by 1.5 V for a positive gate bias stress period of 104 s when compared to a 2.2 V shift for the unannealed TFTs. The performance and stability improvements are attributed to a reduction of the interface trap density and removing of defects states in the band-gap of the a-ZIO.