{"title":"低温退火提高a-ZIO TFT电路的稳定性","authors":"A. Dey, D. Allee","doi":"10.1109/IRPS.2011.5784601","DOIUrl":null,"url":null,"abstract":"Long duration of low temperature thermal anneals show performance and stability enhancement for low-temperature fabricated amorphous zinc-indium-oxide (a-ZIO) thin-film-transistors (TFTs). The turn-on voltage (Von) of 50 hour annealed TFTs shifts by 1.5 V for a positive gate bias stress period of 104 s when compared to a 2.2 V shift for the unannealed TFTs. The performance and stability improvements are attributed to a reduction of the interface trap density and removing of defects states in the band-gap of the a-ZIO.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Stability improvement of a-ZIO TFT circuits using low temperature anneal\",\"authors\":\"A. Dey, D. Allee\",\"doi\":\"10.1109/IRPS.2011.5784601\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Long duration of low temperature thermal anneals show performance and stability enhancement for low-temperature fabricated amorphous zinc-indium-oxide (a-ZIO) thin-film-transistors (TFTs). The turn-on voltage (Von) of 50 hour annealed TFTs shifts by 1.5 V for a positive gate bias stress period of 104 s when compared to a 2.2 V shift for the unannealed TFTs. The performance and stability improvements are attributed to a reduction of the interface trap density and removing of defects states in the band-gap of the a-ZIO.\",\"PeriodicalId\":242672,\"journal\":{\"name\":\"2011 International Reliability Physics Symposium\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRPS.2011.5784601\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2011.5784601","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Stability improvement of a-ZIO TFT circuits using low temperature anneal
Long duration of low temperature thermal anneals show performance and stability enhancement for low-temperature fabricated amorphous zinc-indium-oxide (a-ZIO) thin-film-transistors (TFTs). The turn-on voltage (Von) of 50 hour annealed TFTs shifts by 1.5 V for a positive gate bias stress period of 104 s when compared to a 2.2 V shift for the unannealed TFTs. The performance and stability improvements are attributed to a reduction of the interface trap density and removing of defects states in the band-gap of the a-ZIO.
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