2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)最新文献

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Integrating 8nm Self-Aligned Tip-to-Tip to Enable 4-track Standard Cell Architecture as Scaling Booster 集成8nm自对准尖端,使4轨道标准单元架构作为缩放助推器
P. Marien, V. V. Gonzalez, S. Choudhury, D. Radisic, S. Decoster, S. Kundu, Y. Hermans, B. Kenens, H. De Coster, E. Sanchez, A. Peter, A. S. Marquez, N. Jourdan, D. Batuk, J. Ryckaert, G. Murdoch, S. Park, Z. Tokei
{"title":"Integrating 8nm Self-Aligned Tip-to-Tip to Enable 4-track Standard Cell Architecture as Scaling Booster","authors":"P. Marien, V. V. Gonzalez, S. Choudhury, D. Radisic, S. Decoster, S. Kundu, Y. Hermans, B. Kenens, H. De Coster, E. Sanchez, A. Peter, A. S. Marquez, N. Jourdan, D. Batuk, J. Ryckaert, G. Murdoch, S. Park, Z. Tokei","doi":"10.1109/IITC/MAM57687.2023.10154710","DOIUrl":"https://doi.org/10.1109/IITC/MAM57687.2023.10154710","url":null,"abstract":"As further scaling of standard cells (SC) continues, new innovative techniques are required to the keep pursuing Moore’s law. Middle-of-line (MOL) scaling boosters are one of the most critical modules to scale standard cells. In this work, we present new morphological and first-time electrical data of 8 nm self-aligned tip-to-tip (T2T) of MOL metal layer as a cell boundary to enable Vertical-Horizontal-Vertical (VHV) cell architecture. This will be the key feature to further downscale standard cell height from 5 to 4 tracks. A VintB space of 8.3 nm with standard deviation of 1.6 nm was achieved. For the M0B, a T2T of 5.9 nm with a standard deviation of 1.6 nm was achieved. Electrically a M0B T2T leakage of <1e–10A/m was obtained on 14% of the measured sites for 8 nm T2T, 30% for 10 nm T2T and 40% for 12 nm T2T.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115597012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automatic Detection of Via Arrays in AFM Images for CMP Dishing Evaluation 用于CMP碟形评价的AFM图像中通孔阵列的自动检测
A. Zienert, Jan Langer, Doreen Hensel, L. Hofmann, K. Gottfried, J. Schuster
{"title":"Automatic Detection of Via Arrays in AFM Images for CMP Dishing Evaluation","authors":"A. Zienert, Jan Langer, Doreen Hensel, L. Hofmann, K. Gottfried, J. Schuster","doi":"10.1109/IITC/MAM57687.2023.10154637","DOIUrl":"https://doi.org/10.1109/IITC/MAM57687.2023.10154637","url":null,"abstract":"We present an efficient algorithm for the detection of array-like patterns of circular vias in AFM images. It combines a new variant of the Hough transformation with an efficient implementation of brute-force search to ensure good results and high performance, compared to a simple intuitive approach. A set of manually labeled benchmark data is used to systematically evaluate the accuracy and improve the algorithm. We apply the new via detection method to measure dishing in AFM images of copper vias after CMP.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117207211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improving uniformity of 3-level High Aspect Ratio Supervias 提高三级高纵横比监控的均匀性
D. Montero, P. Marien, Y. Hermans, V. Vega-Gonzalez, Y. Feurprier, N. Oikawa, N. Buccheri, C. Wu, G. Martinez, D. Batuk, H. Puliyalil, S. Decoster, K. Kumar, F. Lazzarino, G. Murdoch, S. Park, Z. Tokei
{"title":"Improving uniformity of 3-level High Aspect Ratio Supervias","authors":"D. Montero, P. Marien, Y. Hermans, V. Vega-Gonzalez, Y. Feurprier, N. Oikawa, N. Buccheri, C. Wu, G. Martinez, D. Batuk, H. Puliyalil, S. Decoster, K. Kumar, F. Lazzarino, G. Murdoch, S. Park, Z. Tokei","doi":"10.1109/IITC/MAM57687.2023.10154787","DOIUrl":"https://doi.org/10.1109/IITC/MAM57687.2023.10154787","url":null,"abstract":"High aspect-ratio (AR) 3-level Supervias (SV), with a minimum bottom CD of 12.1 nm, AR = 9.4 and with > 93 % electrically active SV are successfully integrated in a Back-End of Line (BEOL) test vehicle with Metal Pitch 36. 3-level SV directly connects Mx with MX+3 metal layers, without connecting to the intermediate two metal layers and is a potential scaling booster for future technology nodes. An SiOCH material (low-k) is chosen as the main dielectric layer, and barrierless Ru as metal. Supervias are patterned following a SV-first, dual damascene integration flow. In this work, the effect of the trench etch in the already patterned SV is explored, and an improved dual damascene process is proposed. The goal is to enhance the electrical yield while keeping high aspect ratios with low bottom CD, to keep Supervias relevant for future advanced nodes.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117269409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Holistic Approach to System Design Technology Co-Optimization for Deep Single Digit Nodes 深度个位数节点系统设计技术协同优化的整体方法
S. S. Song, Gaurav Gupta, Ying-Hao Hsieh, Chun Cheng, S. Ekbote, N. Stevens-Yu, David Greenlaw, Steve Molloy
{"title":"A Holistic Approach to System Design Technology Co-Optimization for Deep Single Digit Nodes","authors":"S. S. Song, Gaurav Gupta, Ying-Hao Hsieh, Chun Cheng, S. Ekbote, N. Stevens-Yu, David Greenlaw, Steve Molloy","doi":"10.1109/IITC/MAM57687.2023.10154687","DOIUrl":"https://doi.org/10.1109/IITC/MAM57687.2023.10154687","url":null,"abstract":"The increasing complexity of process technology and demand for computing have led to unsustainable chip costs with marginal performance and power improvement. SDTCO (System Design Technology Co-Optimization) is proposed to address this cost and performance issues. This paper reviews the key SDTCO knobs to improve the PPACt (Power Performance Area Cost and Time-to-market), covering the novel processes and interrelationships between different knobs and key performance indicators in MOL (Middle of Line) and BEOL (Back End of Line) process. Holistic SDTCO evaluation and optimization methods taking from unit process to system level KPI (Key Performance Index) are needed for sustainable cost per transistor scaling and reasonable power and performance improvement.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"299302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123444946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Intermetallic Compounds as Alternatives to Copper for Advanced Interconnect Metallization 金属间化合物作为铜的替代品用于高级互连金属化
C. Adelmann, J. Soulie, J. Scheerder, C. Fleischmann, K. Sankaran, G. Pourtois, J. Swerts, Z. Tokei
{"title":"Intermetallic Compounds as Alternatives to Copper for Advanced Interconnect Metallization","authors":"C. Adelmann, J. Soulie, J. Scheerder, C. Fleischmann, K. Sankaran, G. Pourtois, J. Swerts, Z. Tokei","doi":"10.1109/IITC/MAM57687.2023.10154839","DOIUrl":"https://doi.org/10.1109/IITC/MAM57687.2023.10154839","url":null,"abstract":"Recently, the search for alternative metallization schemes beyond Cu has been extended from elemental metals to binary and ternary intermetallics. Here, we review our material selection process for binary intermetallic compounds and discuss the additional complexities to understand the transport in such metals with respect to elemental metals. A simple but practical resistance model for binary compounds is proposed by extending the Mayadas-Shatzkes model for ordered intermetallics.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126275137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measuring Ion Energy Distributions by Retarding Field Energy Analyzer and Using Low-Energy Ions for Si-ALE by Cl2 用缓速场能量分析仪测量离子能量分布,用低能量离子对Cl2进行Si-ALE
Nils Dittmar, B. Berger, M. Melzer, M. Küchler, C. Meinecke, M. Haase, D. Reuter
{"title":"Measuring Ion Energy Distributions by Retarding Field Energy Analyzer and Using Low-Energy Ions for Si-ALE by Cl2","authors":"Nils Dittmar, B. Berger, M. Melzer, M. Küchler, C. Meinecke, M. Haase, D. Reuter","doi":"10.1109/IITC/MAM57687.2023.10154736","DOIUrl":"https://doi.org/10.1109/IITC/MAM57687.2023.10154736","url":null,"abstract":"To minimize etching damage of the underlying material, atomic layer etching (ALE) with low-energy ions was used for structuring silicon. The ion energy distribution was determined using a retarding field energy analyzer. The etching tool achieved a maximal ion energy of 136 eV at 140 W bias power and an average ion energy of 11.1 eV without applied bias power. The plasma-enhanced ALE included a Cl2 adsorption and an Ar desorption step. The bias power was varied between 8 W and 22 W. The observed etch per cycle (averaged over 30 cycles) was minimal (~0.3 nm) at 8 W (~12 eV) and maximal (~14 nm) at 19 W (~23 eV) bias power. Atomic force microscopy measurements revealed rough etch grounds.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"501 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127920034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Study of Resistivity Control for Subtractive Interconnects Using Ruthenium 用钌控制减法互连电阻率的研究
Jack Rogers, H. Aizawa, Nicholas A. Joy, S. Rogalskyj, Rin Lee, Kenichi Imakita, K. Yu
{"title":"A Study of Resistivity Control for Subtractive Interconnects Using Ruthenium","authors":"Jack Rogers, H. Aizawa, Nicholas A. Joy, S. Rogalskyj, Rin Lee, Kenichi Imakita, K. Yu","doi":"10.1109/IITC/MAM57687.2023.10154851","DOIUrl":"https://doi.org/10.1109/IITC/MAM57687.2023.10154851","url":null,"abstract":"Ruthenium is a candidate metal to replace copper for BEOL metal interconnects due to its electrical characteristics and direct etch capabilities. Electrical performance is a major consideration for “beyond copper” metals – especially as the line CD approaches 10nm where copper line resistance increases significantly. In this report we show the impacts of liner material and direct metal etching on blanket and patterned wafer resistance, and use supporting physical and chemical analyses to confirm methods from both processes to decrease ruthenium resistivity.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128574258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling a Wet Wafer Surface Processing Chain 湿晶圆片表面加工链建模
Max Huber, A. Zienert, J. Schuster
{"title":"Modeling a Wet Wafer Surface Processing Chain","authors":"Max Huber, A. Zienert, J. Schuster","doi":"10.1109/IITC/MAM57687.2023.10154873","DOIUrl":"https://doi.org/10.1109/IITC/MAM57687.2023.10154873","url":null,"abstract":"We present a wet wafer surface processing chain model that allows process engineers to optimize their technological processes concerning total process time. As an example, we study the water layer thickness on wafers from rinsing to the conditions directly before bonding. As part of this process, we focus on simulations of the wafer temperature change in a bond chamber during evacuation. The gas temperature change is calculated using a literature-known model. With this, the wafer surface temperature and the temperature profile along the symmetry axis of the wafer are calculated using Newton’s law of cooling and the heat equation, respectively.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130208861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Microsecond UV laser annealing annihilating Ru grains smaller than electron mean free path 微秒紫外激光退火湮没小于电子平均自由程的Ru晶粒
Lu Lu, N. Jourdan, R. Daubriac, T. Tabata, Fabien Rozé, Louis Thuries, F. Cristiano, Z. Tokei
{"title":"Microsecond UV laser annealing annihilating Ru grains smaller than electron mean free path","authors":"Lu Lu, N. Jourdan, R. Daubriac, T. Tabata, Fabien Rozé, Louis Thuries, F. Cristiano, Z. Tokei","doi":"10.1109/IITC/MAM57687.2023.10154669","DOIUrl":"https://doi.org/10.1109/IITC/MAM57687.2023.10154669","url":null,"abstract":"Enlarging metal grain size over electron mean free path is one of the ways to reduce resistivity in BEOL interconnect because it suppresses electron scattering at grain boundaries. In this work, by means of microsecond UV laser annealing (μs UV-LA), the mean grain size of an as-deposited 30-nm-thick Ru thin film has increased from 10.2 nm to 70.1 nm, reducing sheet resistance for 45% without damaging the Ru surface. The results highlight a potential benefit of μs UV-LA on future Ru-based BEOL interconnect.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130619618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Exploring the Benefits of Cryogenic Temperatures for Co and Ru Metallizations 探索低温对钴和钌金属化的好处
D. Tierno, I. Ciofi, O. Pedreira, B. Parvais, K. Croes
{"title":"Exploring the Benefits of Cryogenic Temperatures for Co and Ru Metallizations","authors":"D. Tierno, I. Ciofi, O. Pedreira, B. Parvais, K. Croes","doi":"10.1109/IITC/MAM57687.2023.10154717","DOIUrl":"https://doi.org/10.1109/IITC/MAM57687.2023.10154717","url":null,"abstract":"We benchmarked Co and Ru metallizations against Cu at cryogenic temperatures (5K-300K) by using imec resistivity model and actual interconnects, with widths between 14 and 64 nm. We observed a decrease in resistance as temperature decreases, with Ru and Co exhibiting the largest drop (~50%) due to their larger Temperature Coefficients of Resistance (TCR). For 20nm-wide lines, the calculated TCR was ~2000 ppm/°C for Ru and Co compared to ~1000 ppm/°C for Cu. However, we show that only Ru outperforms Cu, with the cross-over occurring at 100K for 26nm-wide lines, potentially boosting the performances of systems operating at cryogenic temperatures.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124920262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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