P. Marien, V. V. Gonzalez, S. Choudhury, D. Radisic, S. Decoster, S. Kundu, Y. Hermans, B. Kenens, H. De Coster, E. Sanchez, A. Peter, A. S. Marquez, N. Jourdan, D. Batuk, J. Ryckaert, G. Murdoch, S. Park, Z. Tokei
{"title":"集成8nm自对准尖端,使4轨道标准单元架构作为缩放助推器","authors":"P. Marien, V. V. Gonzalez, S. Choudhury, D. Radisic, S. Decoster, S. Kundu, Y. Hermans, B. Kenens, H. De Coster, E. Sanchez, A. Peter, A. S. Marquez, N. Jourdan, D. Batuk, J. Ryckaert, G. Murdoch, S. Park, Z. Tokei","doi":"10.1109/IITC/MAM57687.2023.10154710","DOIUrl":null,"url":null,"abstract":"As further scaling of standard cells (SC) continues, new innovative techniques are required to the keep pursuing Moore’s law. Middle-of-line (MOL) scaling boosters are one of the most critical modules to scale standard cells. In this work, we present new morphological and first-time electrical data of 8 nm self-aligned tip-to-tip (T2T) of MOL metal layer as a cell boundary to enable Vertical-Horizontal-Vertical (VHV) cell architecture. This will be the key feature to further downscale standard cell height from 5 to 4 tracks. A VintB space of 8.3 nm with standard deviation of 1.6 nm was achieved. For the M0B, a T2T of 5.9 nm with a standard deviation of 1.6 nm was achieved. Electrically a M0B T2T leakage of <1e–10A/m was obtained on 14% of the measured sites for 8 nm T2T, 30% for 10 nm T2T and 40% for 12 nm T2T.","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Integrating 8nm Self-Aligned Tip-to-Tip to Enable 4-track Standard Cell Architecture as Scaling Booster\",\"authors\":\"P. Marien, V. V. Gonzalez, S. Choudhury, D. Radisic, S. Decoster, S. Kundu, Y. Hermans, B. Kenens, H. De Coster, E. Sanchez, A. Peter, A. S. Marquez, N. Jourdan, D. Batuk, J. Ryckaert, G. Murdoch, S. Park, Z. Tokei\",\"doi\":\"10.1109/IITC/MAM57687.2023.10154710\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As further scaling of standard cells (SC) continues, new innovative techniques are required to the keep pursuing Moore’s law. Middle-of-line (MOL) scaling boosters are one of the most critical modules to scale standard cells. In this work, we present new morphological and first-time electrical data of 8 nm self-aligned tip-to-tip (T2T) of MOL metal layer as a cell boundary to enable Vertical-Horizontal-Vertical (VHV) cell architecture. This will be the key feature to further downscale standard cell height from 5 to 4 tracks. A VintB space of 8.3 nm with standard deviation of 1.6 nm was achieved. For the M0B, a T2T of 5.9 nm with a standard deviation of 1.6 nm was achieved. Electrically a M0B T2T leakage of <1e–10A/m was obtained on 14% of the measured sites for 8 nm T2T, 30% for 10 nm T2T and 40% for 12 nm T2T.\",\"PeriodicalId\":241835,\"journal\":{\"name\":\"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC/MAM57687.2023.10154710\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC/MAM57687.2023.10154710","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Integrating 8nm Self-Aligned Tip-to-Tip to Enable 4-track Standard Cell Architecture as Scaling Booster
As further scaling of standard cells (SC) continues, new innovative techniques are required to the keep pursuing Moore’s law. Middle-of-line (MOL) scaling boosters are one of the most critical modules to scale standard cells. In this work, we present new morphological and first-time electrical data of 8 nm self-aligned tip-to-tip (T2T) of MOL metal layer as a cell boundary to enable Vertical-Horizontal-Vertical (VHV) cell architecture. This will be the key feature to further downscale standard cell height from 5 to 4 tracks. A VintB space of 8.3 nm with standard deviation of 1.6 nm was achieved. For the M0B, a T2T of 5.9 nm with a standard deviation of 1.6 nm was achieved. Electrically a M0B T2T leakage of <1e–10A/m was obtained on 14% of the measured sites for 8 nm T2T, 30% for 10 nm T2T and 40% for 12 nm T2T.