Ming Li, Tony Tang, Jie Chen, P. Litmanen, S. Akhtar, R. Murugan
{"title":"Silicon-package co-design of a 45nm 200MHz bandwidth CMOS RF-to-Serdes transceiver system on chip (SoC)","authors":"Ming Li, Tony Tang, Jie Chen, P. Litmanen, S. Akhtar, R. Murugan","doi":"10.1109/EPEPS.2016.7835406","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835406","url":null,"abstract":"In this paper we detail the silicon-package electrical co-design of a 45nm CMOS, 400MHz to 4GHz, 3GPP TDD & FDD, RF-to-Serdes base station transceiver system on chip (SoC). Electrical optimization of the silicon-package RF paths, to achieve desired performance, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation flow. Laboratory measurements, on a real SoC system, are presented that validate the integrity of the modeling and simulation methodology.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128246919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Techniques for detection of package issues in chip power integrity closure","authors":"Mahendrasing Patil, Wilson Leung, W. Liew","doi":"10.1109/EPEPS.2016.7835422","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835422","url":null,"abstract":"Ever increasing need for better performance, die size reduction to aid cost saving and achieving schedule targets has challenged chip designers in multiple spaces. One such very important area is delivering required voltage to on die circuits through robust power grid. Designers have to make some tradeoffs to meet design requirements amid different constraints. Some of these tradeoffs if not well assessed can cause design failures. Through this write-up, we present assessment scheme which can bring out package power plane weaknesses by doing chip-package power delivery network (PDN) analysis.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127231991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electrical modeling and analysis of 3D Neuromorphic IC with Monolithic Inter-tier Vias","authors":"Hongyu An, M. Ehsan, Zhen Zhou, Yang Yi","doi":"10.1109/EPEPS.2016.7835424","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835424","url":null,"abstract":"Neuromorphic computing is an emerging computing technology which utilizes very-large-scale integration (VLSI) technology to mimic neuro-biological architectures present in the nervous system. It promises the realization of parallel computing with extremely low power consumption. To fully take advantage of this computing technology, its scalability and complexity need to be extended beyond its current two dimensional (2D) CMOS fabrication and package technology. In this paper, a three dimensional integrated circuit (3D-IC) technology, which employs Monolithic Inter-tier Via (MIV) and memristor, is proposed to further miniaturize the system and reduce the power consumption. In this work, the building block of the 3D-IC is modeled. In addition, the impact of the crosstalk between the memristor and the MIV is discussed","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127960664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Loewner Matrix interpolation for noisy S-parameter data","authors":"M. Kabir, Y. Xiao, R. Khazaka","doi":"10.1109/EPEPS.2016.7835426","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835426","url":null,"abstract":"Loewner Matrix (LM) interpolation technique was proposed as an efficient macromodeling approach compared to state of the art technologies. However, the method becomes inaccurate in presence of noise as it interpolates noise itself. In this paper, we propose a LM interpolation technique suitable for extracting an accurate and passive macromodel from noisy S-parameter data. An order searching algorithm to find the most accurate model maintaining stability is proposed first. Then we propose a least-square approximation based correction on the macromodel. Finally, the passivity of the model is ensured by using a Hamiltonian Matrix Pencil perturbation scheme. The advantages of the proposed approach is illustrated using one full-wave example.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126622201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A stochastic collocation technique for time-domain variability analysis of active circuits","authors":"K. Guo, F. Ferranti, B. Nouri, M. Nakhla","doi":"10.1109/EPEPS.2016.7835415","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835415","url":null,"abstract":"A novel method is presented for time-domain statistical analysis of large active circuits with multiple stochastic parameters. It is based on a stability-preserving model order reduction algorithm coupled with stochastic collocation schemes. Pertinent numerical results validate the proposed method.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114947370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Hejase, P. Paladhi, R. Krabbenhoft, Zhaoqing Chen, Junyan Tang, D. Boday
{"title":"A neural network based method for predicting PCB glass weave induced skew","authors":"J. Hejase, P. Paladhi, R. Krabbenhoft, Zhaoqing Chen, Junyan Tang, D. Boday","doi":"10.1109/EPEPS.2016.7835439","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835439","url":null,"abstract":"This paper proposes the use of a neural network based tool to predict the skew factor of PCB laminate differential channel designs. A multitude of differential stripline design scenarios are 3D modelled, each with a different expected within differential pair skew factor. The modelled data is used to train a neural network. The neural network is tested using an unseen set of design data in order to evaluate the goodness of its predictions. Preliminary results show this machine learned technique to be a viable way to predict PCB glass weave skew without the need to resort to intensive 3D modelling. This method has potential to shorten design cycles and simplify analysis while still achieving good simulation accuracy.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125664041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance modeling and optimization for on-chip interconnects in cross-bar ReRAM memory arrays","authors":"J. Mohseni, C. Pan, A. Naeemi","doi":"10.1109/EPEPS.2016.7835434","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835434","url":null,"abstract":"Performance modeling and optimization for on-chip interconnects in resistive RAM (ReRAM) arrays are presented for two memory design technologies of 1T1R and cross-bar arrays. Different memristor characteristics, cell structures and subarray design schemes are investigated to minimize the overall delay and energy-delay product.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116302156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A method to assess the radiated susceptibility of printed circuit boards","authors":"G. Zhu, W. Thiel, J. Eric Bracken","doi":"10.1109/EPEPS.2016.7835431","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835431","url":null,"abstract":"Printed circuit boards (PCB) are subject to external electromagnetic interference. A validation tool to efficiently predict the worst-case induced voltages and currents is invaluable in the process of making PCB designs pass the immunity test for electromagnetic compliance. This paper proposes to use a 2.5-D hybrid finite-element-method (FEM) solver to characterize the radiated far field and use the reciprocity-based method to calculate the induced port voltages and currents due to an incident plane wave. This method can be used to analyze any full-size PCB. Good agreement with the results from a 3-D full-wave FEM is obtained at low frequencies, where the 2.5-D assumption for the fields in the PCB applies. Furthermore, the calculation time and memory consumption are significantly reduced.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114496913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"EMI modeling and correlation in a highly integrated package design","authors":"Sayed Mobin, G. Kumar, D. de Araujo, S. McKinney","doi":"10.1109/EPEPS.2016.7835430","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835430","url":null,"abstract":"Electromagnetic emission must be properly addressed in complex multi-chip packages (MCM) due to highly miniaturized form-factor requirements. Such modules induce electric and magnetic fields due to high frequency current paths, and if not contained within a susceptible limit, can cause other electronic components to malfunction or compliance failure. Testing for electromagnetic interference (EMI) in the lab after the system is built could be too late. This paper presents an approach to understand the possible EMI sources in a highly integrated complex package system. An EMI simulation methodology has been developed and correlation to near-field measurements is used to establish the accuracy of the simulation. A full wave 3D solver was used to perform the EMI simulation in frequency domain. The emissions were also measured using near-field probes within a shielded chamber. Good correlation was achieved between the measurements and simulations, suggesting benefits of the proposed methodology.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125189819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast parameter extraction for transmission lines with arbitrarily-shaped conductors and dielectrics using the contour integral method","authors":"U. Patel, S. Hum, P. Triverio","doi":"10.1109/EPEPS.2016.7835448","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835448","url":null,"abstract":"This paper presents an accurate surface formulation based on the contour integral method and the Dirichlet-to-Neumann operator to calculate the impedance and admittance parameters of transmission lines of arbitrary shape. The formulation only requires a discretization of the boundaries of the conductors and dielectrics, as opposed to the entire cross-section, which results in fast computations.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117194666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}