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2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)最新文献

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E-shape resonator dualband common mode filter e型谐振器双带共模滤波器
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835409
C. Lin, Yang-Chih Huang, Tzong-Lin Wu
{"title":"E-shape resonator dualband common mode filter","authors":"C. Lin, Yang-Chih Huang, Tzong-Lin Wu","doi":"10.1109/EPEPS.2016.7835409","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835409","url":null,"abstract":"An E-shape resonator dualband common mode filter is introduced in this paper. The proposed design features the advantages of two-layer printed circuit board design with solid ground plane. Furthermore, the equivalent common mode circuit of coupled step impedance quarter-wavelength resonator improves the common mode suppression performance.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126801425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient transient full-wave analysis of high-speed interconnects in multilayer PCBs 多层pcb中高速互连的高效瞬态全波分析
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835445
A. Akbarzadeh-Sharbaf, D. Giannacopoulos
{"title":"Efficient transient full-wave analysis of high-speed interconnects in multilayer PCBs","authors":"A. Akbarzadeh-Sharbaf, D. Giannacopoulos","doi":"10.1109/EPEPS.2016.7835445","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835445","url":null,"abstract":"A new approach to efficiently simulate 3-D high-speed multilayer printed circuit boards (PCBs) using the finite-element time-domain (FETD) method is proposed. The method is based on the discretization of these structures using multiple layers of prism finite elements. In order to eliminate coupling between different layers in the mass matrix, a combined exact/approximate numerical integration technique is applied to the finite element matrices. This makes the final mass matrix fully block-diagonal and greatly reduces the inversion/factorization cost and time. The formulation is readily extended to lossy materials without any additional adverse effect on the stability condition.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122446404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scalable and broadband modeling of coupled on-chip spiral inductors up to 110 GHz 高达110 GHz的耦合片上螺旋电感的可扩展和宽带建模
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835410
Lei Zheng, Andrew R. Ferrara, A. Weisshaar
{"title":"Scalable and broadband modeling of coupled on-chip spiral inductors up to 110 GHz","authors":"Lei Zheng, Andrew R. Ferrara, A. Weisshaar","doi":"10.1109/EPEPS.2016.7835410","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835410","url":null,"abstract":"Hub paper presents a scalable model capturing the magnetic coupling between adjacent on-chip spiral Inductors at frequencies from DC up to 110 GHz. The scalable model is comprised of ideal frequency-independent circuit elements. The element values are given by closed-form expressions In terms of the layout and process parameters. We have applied the modeling methodology to fabricated coupled on-chip inductors and verified the model accuracy through both full-wave EM simulation and measurement. The scalable model is fully compatible with common circuit simulators including Spice and ADS.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122737932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PCB stack-up design and optimization for next generation speeds 下一代速度的PCB堆叠设计和优化
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835440
Chun-Lin Liao, B. Mutnury, Ching-Huei Chen, Yi-Jyun Lee
{"title":"PCB stack-up design and optimization for next generation speeds","authors":"Chun-Lin Liao, B. Mutnury, Ching-Huei Chen, Yi-Jyun Lee","doi":"10.1109/EPEPS.2016.7835440","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835440","url":null,"abstract":"An efficient empirical simulation tool was presented to predict the transmission line performance of coupled differential microstrip and strip lines. Based on the Artificial Neural Network (ANN) method, the predicted transmission line performances were accurate and were suitable for printed circuit board (PCB) stack-up design. Design examples were presented how this tool helping on differential strip line structure parameters design and predicting their performance range with the structure parameters variation.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116588164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Radiation compatible ports and loads for the PEEC method PEEC方法的辐射兼容端口和负载
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835429
Y. S. Cao, L. J. Jiang, A. Ruehli, J. Fan, J. Drewniak
{"title":"Radiation compatible ports and loads for the PEEC method","authors":"Y. S. Cao, L. J. Jiang, A. Ruehli, J. Fan, J. Drewniak","doi":"10.1109/EPEPS.2016.7835429","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835429","url":null,"abstract":"The partial element equivalent circuit method (PEEC) has been popularly used for signal integrity and power integrity. Its port setup usually only includes conductive effects in the format of current sources or voltage sources. However, its radiation effect was neither included nor studied. In this paper, for the first time we provide novel solutions to approximate the radiation contributions from the port and load setups of PEEC. They serve to compensate the accuracy of electromagnetic radiation analysis based on PEEC approach. The proposed radiation compatible ports and loads can be easily applicable to EMI related analysis.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126527628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Drawbacks and possible improvements of Short Pulse Propagation technique 短脉冲传播技术的缺陷与改进
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835437
Y. Shlepnev, Yongjin Choi, Chris. Cheng, Y. Damgaci
{"title":"Drawbacks and possible improvements of Short Pulse Propagation technique","authors":"Y. Shlepnev, Yongjin Choi, Chris. Cheng, Y. Damgaci","doi":"10.1109/EPEPS.2016.7835437","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835437","url":null,"abstract":"Short Pulse Propagation (SPP) technique for characterisation of PCB and packaging interconnect losses and dispersion was introduced in early 90-s and standardized by the Institute of Printed Circuits or IPC [IPC-TM-650]. It was successfully used to build broadband models for dielectrics and conductor roughness up to 30 GHz. Though, it is not widely used and multiple new material characterisation techniques were recently proposed. Is SPP useful for 30 Gbps interconnect design and manufacturing? This paper analyses advantages and drawbacks of the original SPP technique and suggests some simplifications and improvements. It is shown that the number of characterisation steps can be substantially reduced without loss of accuracy. To reduce the sensitivity to the connector and launch reflections and improve accuracy, it is also suggested to use S-parameters instead of TDT pulse responses.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130108730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Toward predictive modeling of full-size packages with layered-medium integral-equation methods 分层介质积分方程方法在全尺寸封装预测建模中的应用
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835446
C. Liu, A. Menshov, V. Subramanian, K. Aygün, H. Braunisch, V. Okhmatovski, A. Yılmaz
{"title":"Toward predictive modeling of full-size packages with layered-medium integral-equation methods","authors":"C. Liu, A. Menshov, V. Subramanian, K. Aygün, H. Braunisch, V. Okhmatovski, A. Yılmaz","doi":"10.1109/EPEPS.2016.7835446","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835446","url":null,"abstract":"Layered-medium integral-equation (LMIE) methods that can confront the multiscale problems encountered in electromagnetic modeling of electronic packages are presented. The methods include (i) an impedance-boundary condition (IBC) formulation for modeling conductor thickness, roughness, and finite conductivity, (ii) non-radiating lumped-port models for extracting network parameters, and (iii) FFT based iterative and hierarchical-matrix (ℋ-matrix) based direct algorithms for efficiently solving the resulting systems of equations. The methods are used to analyze increasingly higher fidelity models of a benchmark packaging interconnect structure; the results are validated with measurements; and the tradeoff between increased model fidelity and computational costs are quantified.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134633411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
RDL and interposer design for DiRAM4 interfaces DiRAM4接口的RDL和中间层设计
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835408
T. Nigussie, P. Franzon
{"title":"RDL and interposer design for DiRAM4 interfaces","authors":"T. Nigussie, P. Franzon","doi":"10.1109/EPEPS.2016.7835408","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835408","url":null,"abstract":"This paper presents results of signal integrity study conducted on two packaging designs: redistribution layer (RDL) for face-to-face stacking and 2.5D interposer for lateral connection of four processor chips with high performance memory die having a bandwidth of 4Tb/s.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129767889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Loewner-based macromodeling with exact interpolation constraints 具有精确插值约束的基于loewner的宏建模
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835414
S. Lefteriu, S. Grivet-Talocia
{"title":"Loewner-based macromodeling with exact interpolation constraints","authors":"S. Lefteriu, S. Grivet-Talocia","doi":"10.1109/EPEPS.2016.7835414","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835414","url":null,"abstract":"The so-called Loewner framework has been recently revitalized, providing an alternative approach to the more standard Vector Fitting scheme for building compact macromodels of interconnect networks. The matrix approximation process that is embedded in the Loewner method produces however models whose accuracy cannot be locally controlled at a desired frequency point. This paper proposes a simple solution for constraining the model response at any selected frequency value, with emphasis on the DC point. Two application examples illustrate the effectiveness of the approach.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"3 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114040489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Delay rational macromodels of long interconnects using Loewner Matrix 基于Loewner矩阵的长互连延迟理性宏模型
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835428
Mohamed Sahouli, A. Dounavis
{"title":"Delay rational macromodels of long interconnects using Loewner Matrix","authors":"Mohamed Sahouli, A. Dounavis","doi":"10.1109/EPEPS.2016.7835428","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835428","url":null,"abstract":"This paper presents a method to obtain delay-based macromodels of electrically long interconnects from tabulated frequency data. The proposed algorithm first extracts multiple propagation delays and splits the data into single delay regions using a time-frequency decomposition transform. Then, the attenuation losses of each region is approximated using the Loewner Matrix approach. The resulting macromodel is a combination of delay rational approximations. A numerical example is presented to illustrate efficiency of the proposed method compared to traditional Loewner where the delays are not extracted beforehand.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121871851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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