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2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)最新文献

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Flip-chip package for 28G SerDes interface 倒装芯片封装28G SerDes接口
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835407
R. Wenzel, T. Zhou, S. Karako
{"title":"Flip-chip package for 28G SerDes interface","authors":"R. Wenzel, T. Zhou, S. Karako","doi":"10.1109/EPEPS.2016.7835407","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835407","url":null,"abstract":"This paper describes successful flip-chip package design for 28G-capable SerDes interfaces. Design optimization of the multi-layer 3D vertical BGA area is accomplished using an EM solver to obtain the best possible insertion and return losses given manufacturing capabilities. Several different stripline and microstrip pair-to-pair spacings bearing different amounts of coupling were evaluated in terms of eye opening and crosstalk-induced jitter. After full die-to-package-to-board assembly, the performance is measured up to 28G data rate. Both stripline and microstrip pairs were found to exhibit adequate performance.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115356575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A passivity approach to FDTD stability with application to interconnect modeling 时域有限差分稳定性的无源方法及其在互连建模中的应用
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835451
Fadime Bekmambetova, Xinyue Zhang, P. Triverio
{"title":"A passivity approach to FDTD stability with application to interconnect modeling","authors":"Fadime Bekmambetova, Xinyue Zhang, P. Triverio","doi":"10.1109/EPEPS.2016.7835451","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835451","url":null,"abstract":"The application of the Finite Difference Time Domain (FDTD) method to signal and power integrity problems is limited by the large aspect ratio of interconnects and by small skin depth at high frequency, which impose a very fine grid and long simulations. While local grid refinement can be used to overcome this issue, ensuring the stability of the resulting FDTD scheme is not trivial. We present a powerful stability theory for FDTD based on the concept of passivity. The theory is suitable to develop multiresolution FDTD methods with guaranteed stability. A simple and stable subgridding algorithm is derived. Numerical results show its potential for the efficient modeling of skin effect in interconnects.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128538484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A study of load-line effect on power supplies of digital networking processors 数字网络处理器电源负载线效应的研究
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835436
T. Zhou, J. Golab
{"title":"A study of load-line effect on power supplies of digital networking processors","authors":"T. Zhou, J. Golab","doi":"10.1109/EPEPS.2016.7835436","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835436","url":null,"abstract":"Digital networking processor power supplies typically have voltage sense points at die level so that the die level voltages are regulated and kept at constant DC levels. In this paper, we studied the load-line effect on the power supplies by simulations and lab measurements. We found that the total dissipated power for digital networking processors can be reduced by the introduction of the load-line effect in the regulation loop. The thermal design point of the system could be relaxed by introducing load-line operation without compromising the performance of these processors.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124079238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Guard band reduction via dynamic voltage sensing and reference setting schemes in power gated applications 在功率门控应用中，通过动态电压传感和参考设置方案减少保护带
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835417
A. Jain, Sameer Shekhar
{"title":"Guard band reduction via dynamic voltage sensing and reference setting schemes in power gated applications","authors":"A. Jain, Sameer Shekhar","doi":"10.1109/EPEPS.2016.7835417","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835417","url":null,"abstract":"Use of power gates for leakage power reduction comes at the expense of higher DC and AC load lines due to location of voltage regulator sense point before the power gate and choice reference voltage to guarantee minimum voltage across all power gate and load conditions. This paper proposes schemes to dynamically change both the sense voltage and the reference voltage to reduce AC & DC load lines and consequently voltage guard bands. The simultaneous choice in sense and reference centers the load voltage variation between different gated domains providing an optimal solution without increase in maximum voltages. Application to client microprocessors show a benefit of a few tens of milli-Volts.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127964762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SI-PI analysis and compliance test of HDMI 1.4b serial channel with IBIS-AMI HDMI 1.4b串行通道与IBIS-AMI的SI-PI分析及符合性测试
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835420
A. Pandey
{"title":"SI-PI analysis and compliance test of HDMI 1.4b serial channel with IBIS-AMI","authors":"A. Pandey","doi":"10.1109/EPEPS.2016.7835420","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835420","url":null,"abstract":"In this paper, signal and power integrity of complete High Definition Multimedia Interface (HDMI) channel with IBIS-AMI model is presented. Gigahertz serialization and deserialization (SERDES) has become a leading inter-chip and inter-board data transmission technique in high-end computing devices. The IBIS-AMI model is used for circuit simulation of high-speed serial interfaces. A 3D frequency-domain simulator (FEM) was used to estimate the channel loss for data bus and HDMI connector. Compliance testing is performed for HDMI channels to ensure channel parameters are meeting HDMI specifications.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128878445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling and design of system-in-package integrated voltage regulator with thermal effects 具有热效应的系统集成稳压器建模与设计
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835419
S. Mueller, A. K. Davis, M. Bellaredj, A. Singh, K. Z. Ahmed, M. Kar, S. Mukhopadhyay, P. Kohl, M. Swaminathan, Y. Wang, J. Wong, S. Bharathi, Y. Mano, A. Beece, B. Fasano, H. F. Moghadam, D. Draper
{"title":"Modeling and design of system-in-package integrated voltage regulator with thermal effects","authors":"S. Mueller, A. K. Davis, M. Bellaredj, A. Singh, K. Z. Ahmed, M. Kar, S. Mukhopadhyay, P. Kohl, M. Swaminathan, Y. Wang, J. Wong, S. Bharathi, Y. Mano, A. Beece, B. Fasano, H. F. Moghadam, D. Draper","doi":"10.1109/EPEPS.2016.7835419","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835419","url":null,"abstract":"This paper demonstrates a new approach to model the impact of thermal effects on the efficiency of integrated voltage regulators (IVRs) by combining analytical efficiency evaluations with coupled electrical and thermal simulations. An application of the approach shows that a system-in-package solution avoids thermal problems typically observed in other IVR designs. While the evaluation in this paper focuses on the thermal impact on loss in the inductor wiring and the PDN, the developed approach is general enough to also model thermal impacts on the power dissipation in the inductor cores and the buck converter chip.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129816035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Signal integrity analysis of vertical dual port coaxial connector for automotive system 汽车系统垂直双端口同轴连接器信号完整性分析
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835442
Dong-Hyun Kim, Hyunsuk Lee, Hongseok Kim, Jonghoon J. Kim, Joungho Kim, Jung-min Park, Ji-Min Kim, Kyung-Nam Lee, Jong-Hoon Woo, H. Kwon, Hoon Kim
{"title":"Signal integrity analysis of vertical dual port coaxial connector for automotive system","authors":"Dong-Hyun Kim, Hyunsuk Lee, Hongseok Kim, Jonghoon J. Kim, Joungho Kim, Jung-min Park, Ji-Min Kim, Kyung-Nam Lee, Jong-Hoon Woo, H. Kwon, Hoon Kim","doi":"10.1109/EPEPS.2016.7835442","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835442","url":null,"abstract":"Different designs of vertical dual port coaxial connectors are proposed and analyzed using full wave 3D simulation tool up to 10 GHz. By inserting conducting grounds around the pins, the signal integrity of the vertical dual port coaxial cable connector is improved. The vertical dual port coaxial connector cable assembly can be used to reduce the printed circuit board space required for the connectors and reduce the total cost of coaxial connectors required for automotive system.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130071588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The relationship between Galerkin and collocation methods in statistical transmission line analysis 输电线统计分析中伽辽金法与配置法的关系
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835412
P. Manfredi, D. De Zutter, D. Vande Ginste
{"title":"The relationship between Galerkin and collocation methods in statistical transmission line analysis","authors":"P. Manfredi, D. De Zutter, D. Vande Ginste","doi":"10.1109/EPEPS.2016.7835412","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835412","url":null,"abstract":"This paper discusses the relationship between two standard methods for the stochastic analysis of linear circuits, namely the stochastic Galerkin method (SGM) and the stochastic collocation method (SCM), based on a multidimensional Gaussian quadrature. It is established that the SCM corresponds to an approximate factorization of the SGM, involving matrix polynomials sharing the same coefficients as the pertinent polynomial chaos basis functions. Under certain assumptions, the two methods coincide. These findings are illustrated by means of a frequency-domain simulation of a transmission line circuit.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123175614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
8B9B encoding for crosstalk reduction in a high-speed parallel bus 用于高速并行总线中串扰减少的8B9B编码
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835411
Sunil R. Sudhakaran, R. Newcomb
{"title":"8B9B encoding for crosstalk reduction in a high-speed parallel bus","authors":"Sunil R. Sudhakaran, R. Newcomb","doi":"10.1109/EPEPS.2016.7835411","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835411","url":null,"abstract":"This paper presents a new encoding and corresponding decoding scheme to reduce crosstalk on a high-speed parallel bus. The scheme is based on a modified Fibonacci sequence and is introduced along with potential benefits in some upcoming memory interfaces. The scheme provides appreciable eye opening for interfaces dominated by crosstalk such as existing memory interfaces.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116233764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Power delivery network design and modeling for High Bandwidth Memory (HBM) 高带宽存储器(HBM)供电网络设计与建模
2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI: 10.1109/EPEPS.2016.7835405
Wenjun Shi, Yaping Zhou, Sunil R. Sudhakaran
{"title":"Power delivery network design and modeling for High Bandwidth Memory (HBM)","authors":"Wenjun Shi, Yaping Zhou, Sunil R. Sudhakaran","doi":"10.1109/EPEPS.2016.7835405","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835405","url":null,"abstract":"A modeling method to consider simulation switching noise of HBM and its impact on HBM timing is described. This method combines partial element equivalent circuit model for power delivery network and S-parameters based HBM channel model together in HBM studies.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130478270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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