Flip-chip package for 28G SerDes interface

Abstract

This paper describes successful flip-chip package design for 28G-capable SerDes interfaces. Design optimization of the multi-layer 3D vertical BGA area is accomplished using an EM solver to obtain the best possible insertion and return losses given manufacturing capabilities. Several different stripline and microstrip pair-to-pair spacings bearing different amounts of coupling were evaluated in terms of eye opening and crosstalk-induced jitter. After full die-to-package-to-board assembly, the performance is measured up to 28G data rate. Both stripline and microstrip pairs were found to exhibit adequate performance.