Marco T. Kassis, Yaswanth R. Akaveeti, B. Meyer, R. Khazaka
{"title":"Parallel transient simulation of power delivery networks using model order reduction","authors":"Marco T. Kassis, Yaswanth R. Akaveeti, B. Meyer, R. Khazaka","doi":"10.1109/EPEPS.2016.7835452","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835452","url":null,"abstract":"On-chip power delivery networks have become an important design bottleneck while posing a significant challenge to design automation tools due to their large models. In this paper we propose a method that uses model order reduction methodologies in order to reformulate the simulation as a reduced parallel simulation problem that can take advantage of modern multi-core CPUs. Numerical examples are used to illustrate the accuracy and efficiency of the proposed method.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"10 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131922847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A high-performance global eletromagnetic noise suppression method for 3D TSV SiP","authors":"Yong-Wei Chen, Mu-Shui Zhang, Y. Li","doi":"10.1109/EPEPS.2016.7835423","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835423","url":null,"abstract":"In this paper, we propose a high-performance method to suppress global electromagnetic noise coupling in 3D through silicon via (TSV) system in package (SiP). This technique needs to form a periodic shielding structure in 3D SiP, which consists of contact arrays, grid ground planes and ground TSV array. Contact arrays and grid ground planes can suppress noise coupling in the shallow substrate and ground TSV array suppresses noise coupling in the deep substrate. This method is practical for noise suppression in 3D SiP with heterogeneous integration. Results show that it has a better performance when it is compared to the guard ring method even the working frequency reaches 50 GHz.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123001075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient and robust Dyadic Green's Function evaluation algorithm for the analysis of IC packages and printed circuit boards","authors":"Giacomo Bianconi, Jose' Pinto, Swagato Chakraborty","doi":"10.1109/EPEPS.2016.7835453","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835453","url":null,"abstract":"This paper presents an efficient and accurate methodology for the layered media Green's function evaluation in fully 3D electromagnetic scenarios such as of IC packages and printed circuit boards.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128946801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of wafer-bonding defects on Monolithic 3D integrated circuits","authors":"Abhishek Koneru, S. Kannan, K. Chakrabarty","doi":"10.1109/EPEPS.2016.7835425","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835425","url":null,"abstract":"Monolithic three-dimensional (M3D) integration has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias. We analyze defects that arise due to voids created during the wafer-bonding step in M3D integration. We quantify the impact of these defects on the threshold voltage of a top-layer transistor in an M3D integrated circuit. We also show that wafer-bonding defects can lead to a change in the resistance of inter-layer vias (ILVs), and in some cases, lead to an open in an ILV or a short between two ILVs. We then analyze the impact of these defects on path delays. Our results show that the timing characteristics of an M3D IC can be significantly altered due to the presence of wafer-bonding defects.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"54 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117028231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Anisotropic formulation of hyperbolic polynomial chaos expansion for high-dimensional variability analysis of nonlinear circuits","authors":"Ishan Kapse, Sourajeet Roy","doi":"10.1109/EPEPS.2016.7835433","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835433","url":null,"abstract":"In this paper, a new polynomial chaos (PC) approach for the fast variability analysis of high speed nonlinear circuits is presented. The key feature of this work is the development of an alternative anisotropic hyperbolic scheme to intelligently truncate general PC expansions. This truncation scheme not only prunes the statistically insignificant bases arising from the high degree interactions of the random dimensions but also modulates the maximum degree of expansion along each dimension based on the contribution of that dimension to the response surface. The proposed approach results in a substantially sparser PC expansion for marginal loss of accuracy.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116224270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enlarged cell technique for conformal equivalent circuit model of power delivery network","authors":"T. Sekine, H. Asai","doi":"10.1109/EPEPS.2016.7835432","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835432","url":null,"abstract":"This paper describes a technique to improve a conformal equivalent circuit model for efficient transient analysis of a power delivery network (PDN). The conformal equivalent circuit of the PDN may include small capacitance due to an irregular cell, which has a small conductor area. The small value of the capacitance makes the time step size of an explicit leapfrog scheme be small to ensure its numerical stability condition. The proposed enlarged cell technique is based on enlargement of the conductor area in the irregular cell to derive a larger capacitance and avoid the time step size reduction.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125571650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hang Jin, Erping Li, A. Ruehli, J. Drewniak, B. Archambeault
{"title":"Time domain PDN noise modeling for high performance system","authors":"Hang Jin, Erping Li, A. Ruehli, J. Drewniak, B. Archambeault","doi":"10.1109/EPEPS.2016.7835418","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835418","url":null,"abstract":"In this paper, we investigate the impact of the PDN inductance/impedance as well as the decoupling capacitors location on the initial IC noise voltage drop for a high performance system. To consider a worst case situation for the noise voltage at the integrated circuit (IC) we set the on-chip capacitance to zero. The impact of the delay due to remote location of the decoupling capacitors for fast rise-time current waveforms is also studied.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125866746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel algorithm for computing the zeros of transfer functions by local minima","authors":"Nuzhat Yamin, A. Zadehgol","doi":"10.1109/EPEPS.2016.7835421","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835421","url":null,"abstract":"We present a novel technique for computing the zeros of rational transfer functions in partial fraction form, by finding the local minima of the magnitude of the determinant of a block matrix comprised of state-space sub-matrices and the Laplace variable s. In this paper, the technique is developed for systems with real poles and residues, and successfully applied to a 10th order numerical example. In a separate paper, we further develop the technique to systems with complex-conjugate pairs of poles and residues.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121883491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Machine learning in physical design","authors":"Bowen Li, P. Franzon","doi":"10.1109/EPEPS.2016.7835438","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835438","url":null,"abstract":"Machine learning, a powerful technique for building models, can rapidly provide accurate predictions. Since Integrated Circuit (IC) design and manufacturing have tremendously high complexity and enormous data, there is a surge in adapting machine learning approach in IC Design stages, as machine learning can provide fast predictions. Recently, machine learning has been used in some IC Design stages (e.g. Physical Verification), but not in Physical Design. In this research, machine learning is adapted to Physical Design. Surrogate Modeling is implemented to predict results after GR in Physical Design. Machine learning models for predicting Detailed Route (DR) results using Global Route (GR) results are also discussed. With surrogate models and machine learning methods, circuit performances after Physical Design (e.g. hold violation check and area) would be predicted quickly.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"35 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122519061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mesh-based impedance sensitivity formulation for DC/AC Power Integrity design and diagnosis","authors":"N. Ambasana, B. Nayak, D. Gope","doi":"10.1109/EPEPS.2016.7835416","DOIUrl":"https://doi.org/10.1109/EPEPS.2016.7835416","url":null,"abstract":"Accurate Power Distribution Network (PDN) design is crucial for Signal/Power Integrity (SI/PI) and Electromagnetic Interference (EMI) compliance. Achieving target power-ground (PG) noise levels for low power complex PDNs requires several design and analysis cycles. Although several classes of analysis tools, 2.5D and 3D, are commercially available, the presence of design tools are limited e.g. parametric design space exploration using multiple forward analysis. In this work, a frequency domain mesh-based sensitivity formulation for DC and AC impedance of PDNs is proposed. The two main objectives include: (i) highlighting layout regions to the designer for maximum impact in achieving target specifications and (ii) predicting the results of a design variant with mesh-based sensitivity information from the base-design. The time required for updating the results for the design variant is negligible compared to a complete re-simulation.","PeriodicalId":241629,"journal":{"name":"2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)","volume":"107 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130495238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}