高性能系统的时域PDN噪声建模

2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI:10.1109/EPEPS.2016.7835418

Hang Jin, Erping Li, A. Ruehli, J. Drewniak, B. Archambeault

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引用次数: 0

摘要

在本文中，我们研究了PDN电感/阻抗以及去耦电容位置对高性能系统初始IC噪声压降的影响。为了考虑集成电路(IC)噪声电压的最坏情况，我们将片上电容设置为零。研究了去耦电容位置遥远对快速上升时间电流波形的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Time domain PDN noise modeling for high performance system

In this paper, we investigate the impact of the PDN inductance/impedance as well as the decoupling capacitors location on the initial IC noise voltage drop for a high performance system. To consider a worst case situation for the noise voltage at the integrated circuit (IC) we set the on-chip capacitance to zero. The impact of the delay due to remote location of the decoupling capacitors for fast rise-time current waveforms is also studied.

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来源期刊

2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)

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