Time domain PDN noise modeling for high performance system

Abstract

In this paper, we investigate the impact of the PDN inductance/impedance as well as the decoupling capacitors location on the initial IC noise voltage drop for a high performance system. To consider a worst case situation for the noise voltage at the integrated circuit (IC) we set the on-chip capacitance to zero. The impact of the delay due to remote location of the decoupling capacitors for fast rise-time current waveforms is also studied.