DiRAM4接口的RDL和中间层设计

2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI:10.1109/EPEPS.2016.7835408

T. Nigussie, P. Franzon

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引用次数: 2

摘要

本文介绍了两种封装设计的信号完整性研究结果:用于面对面堆叠的再分配层(RDL)和用于四个处理器芯片横向连接的2.5D中间层，其带宽为4Tb/s的高性能存储芯片。

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RDL and interposer design for DiRAM4 interfaces

This paper presents results of signal integrity study conducted on two packaging designs: redistribution layer (RDL) for face-to-face stacking and 2.5D interposer for lateral connection of four processor chips with high performance memory die having a bandwidth of 4Tb/s.

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来源期刊

2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)

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