Techniques for detection of package issues in chip power integrity closure

Abstract

Ever increasing need for better performance, die size reduction to aid cost saving and achieving schedule targets has challenged chip designers in multiple spaces. One such very important area is delivering required voltage to on die circuits through robust power grid. Designers have to make some tradeoffs to meet design requirements amid different constraints. Some of these tradeoffs if not well assessed can cause design failures. Through this write-up, we present assessment scheme which can bring out package power plane weaknesses by doing chip-package power delivery network (PDN) analysis.