Electrical modeling and analysis of 3D Neuromorphic IC with Monolithic Inter-tier Vias

Abstract

Neuromorphic computing is an emerging computing technology which utilizes very-large-scale integration (VLSI) technology to mimic neuro-biological architectures present in the nervous system. It promises the realization of parallel computing with extremely low power consumption. To fully take advantage of this computing technology, its scalability and complexity need to be extended beyond its current two dimensional (2D) CMOS fabrication and package technology. In this paper, a three dimensional integrated circuit (3D-IC) technology, which employs Monolithic Inter-tier Via (MIV) and memristor, is proposed to further miniaturize the system and reduce the power consumption. In this work, the building block of the 3D-IC is modeled. In addition, the impact of the crosstalk between the memristor and the MIV is discussed