Performance modeling and optimization for on-chip interconnects in cross-bar ReRAM memory arrays

2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI:10.1109/EPEPS.2016.7835434

J. Mohseni, C. Pan, A. Naeemi

引用次数: 0

Abstract

Performance modeling and optimization for on-chip interconnects in resistive RAM (ReRAM) arrays are presented for two memory design technologies of 1T1R and cross-bar arrays. Different memristor characteristics, cell structures and subarray design schemes are investigated to minimize the overall delay and energy-delay product.

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跨条ReRAM存储器阵列片上互连的性能建模和优化

针对1T1R和交叉条阵列两种存储器设计技术，提出了电阻式RAM (ReRAM)阵列片上互连的性能建模和优化方法。研究了不同的忆阻器特性、单元结构和子阵列设计方案，以最小化总体延迟和能量延迟积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)

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