45nm 200MHz带宽CMOS RF-to-Serdes片上收发器系统的硅封装协同设计

2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS) Pub Date : 2016-10-01 DOI:10.1109/EPEPS.2016.7835406

Ming Li, Tony Tang, Jie Chen, P. Litmanen, S. Akhtar, R. Murugan

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引用次数: 5

摘要

在本文中，我们详细介绍了一个45nm CMOS, 400MHz至4GHz, 3GPP TDD和FDD, rf到serdes基站收发器片上系统(SoC)的硅封装电气协同设计。通过耦合电路-电磁协同设计建模和仿真流程，实现了硅封装射频路径的电气优化，以实现所需的性能。在一个真实的SoC系统上进行了实验室测量，验证了建模和仿真方法的完整性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Silicon-package co-design of a 45nm 200MHz bandwidth CMOS RF-to-Serdes transceiver system on chip (SoC)

In this paper we detail the silicon-package electrical co-design of a 45nm CMOS, 400MHz to 4GHz, 3GPP TDD & FDD, RF-to-Serdes base station transceiver system on chip (SoC). Electrical optimization of the silicon-package RF paths, to achieve desired performance, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation flow. Laboratory measurements, on a real SoC system, are presented that validate the integrity of the modeling and simulation methodology.

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来源期刊

2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)

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