发布求助
文献互助 智能选刊 最新文献

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.最新文献

筛选
英文 中文
A single-photon-avalanche-diode 3D imager 单光子雪崩二极管三维成像仪
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541666
D. Stoppa, L. Pancheri, M. Scandiuzzo, M. Malfatti, G. Pedretti, L. Gonzo
{"title":"A single-photon-avalanche-diode 3D imager","authors":"D. Stoppa, L. Pancheri, M. Scandiuzzo, M. Malfatti, G. Pedretti, L. Gonzo","doi":"10.1109/ESSCIR.2005.1541666","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541666","url":null,"abstract":"This paper describes the design and characterization of a 64-pixel array exploiting the high sensitivity offered by single photon avalanche diodes, fabricated in a conventional high-voltage 0.8/spl mu/m CMOS technology, and aimed at three dimensional measurements using the time-of-flight technique. The detection of the incident light signals is performed using a photodiode biased above its breakdown voltage so that an extremely high sensitivity can be achieved exploiting the intrinsic multiplication effect of the avalanche phenomenon. A single photon avalanche diode and dedicated read-out electronics for the arrival-time estimation of incident light pulses have been implemented in a 38/spl times/180-/spl mu/m/sup 2/ pixel. To increase the distance measurement resolution a multiple pulse measurement is used, extracting the mean value of the light pulse arrival-time directly in each pixel; this innovative approach dramatically reduces the dead-time of the pixel read-out, allowing a high frame rate imaging to be achieved. The sensor array provides a range map from 2m to 5m with a precision better than /spl mu/m 0.75% without any external averaging operation.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114201864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
17 GHz receiver in TSLP package for WLAN/ISM applications in 0.13 /spl mu/m CMOS 用于WLAN/ISM应用的TSLP封装的17 GHz接收器，采用0.13 /spl mu/m CMOS
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541577
C. Kienmayer, M. Engl, Aandreas Desch, R. Thüringer, Mohit Berry, M. Tiebout, A. Scholtz, R. Weigel
{"title":"17 GHz receiver in TSLP package for WLAN/ISM applications in 0.13 /spl mu/m CMOS","authors":"C. Kienmayer, M. Engl, Aandreas Desch, R. Thüringer, Mohit Berry, M. Tiebout, A. Scholtz, R. Weigel","doi":"10.1109/ESSCIR.2005.1541577","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541577","url":null,"abstract":"This work presents a fully integrated CMOS receiver in a leadless plastic package (TSLP) for high data rate WLAN applications at 17.2 GHz ISM band. The receiver offers a gain of 35 dB, input 1dB compression point of -49.6 dBm, SSB noise figure of 9.9 dB and an input IP3 of -39.8 dBm. At a power supply of 1.5 V, the receiver, which includes LNA, complex demodulator, VCO, IQ-divider and all RF-buffers, consumes only 245 mW.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133397131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 220mW 14b 40MSPS gain calibrated pipelined ADC 一个220mW 14b 40MSPS增益校准的流水线ADC
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541585
J. Bjørnsen, Øystein Moldsvor, Trond Sæther, T. Ytterdal
{"title":"A 220mW 14b 40MSPS gain calibrated pipelined ADC","authors":"J. Bjørnsen, Øystein Moldsvor, Trond Sæther, T. Ytterdal","doi":"10.1109/ESSCIR.2005.1541585","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541585","url":null,"abstract":"In this paper, a pipelined ADC based on digital calibration of gain errors is presented. The ADC achieves 85dBFS SNDR and 84dBFS SFDR with a 50dB DC gain OTA in the first stage. The calibration algorithm is based on test signal injection. At 40MSPS the power dissipation is 220mW from a 2.5V supply. The ADC is designed in a 0.25/spl mu/m CMOS process and occupies an area of 6.5mm/sup 2/.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133095982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI 一种新的电路拓扑，用于生成和验证体和SOI的数字感测放大器差分
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541637
R. Joshi, Y. Chan
{"title":"A novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI","authors":"R. Joshi, Y. Chan","doi":"10.1109/ESSCIR.2005.1541637","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541637","url":null,"abstract":"In this paper, a novel programmable voltage divider circuit is proposed for converting digital signals to differential (analog) signals which can be used to evaluate differential sense amplifies in the absence of SRAM cells for the first time. The differentials can be programmable and switchable to reverse polarity. A circuit utilizing this scheme is also proposed to test variety of differential circuits having small signal inputs. The digital input is used to generate analog signals to drive the differential circuits; results are then validated digitally to alleviate more complicated testing problems. The novel circuit technique is implemented in hardware and test results are corroborated with simulations. The circuit functions both in bulk and silicon on insulator (SOI) technologies.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123636598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 8Kb domino read SRAM with hit logic and parity checker 带有命中逻辑和奇偶校验器的8Kb骨牌读SRAM
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541634
A. Pelella, A. Tuminaro, R. Freese, Y. Chan
{"title":"A 8Kb domino read SRAM with hit logic and parity checker","authors":"A. Pelella, A. Tuminaro, R. Freese, Y. Chan","doi":"10.1109/ESSCIR.2005.1541634","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541634","url":null,"abstract":"An 8Kb domino read SRAM with hit logic and parity checker, fabricated in a 65nm SOI CMOS technology (Leobandung, 2005), is described. A key feature is the elimination of the traditional sense amplifier to reduce timing and design complexity. The focus of this paper is to demonstrate a memory array, comprised of 6T cells, that can generate near \"rail-to-rail\" bit-line voltage differentials that can be driven off macro without the aid of sense amplifiers. Therefore, short, low capacitance bit-line segments (or sub-arrays) are cascaded together to form larger bit-line structures, achieving performance and density goals with robust operation over a wide range of process and environmental conditions.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116723243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Dynamic state-retention flip flop for fine-grained sleep-transistor scheme 细粒度睡眠晶体管方案的动态状态保持触发器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541580
S. Henzler, Thomas Nirschi, C. Pacha, Peter Spindler, P. Teichmann, M. Fulde, J. Fischer, M. Eireiner, T. Fischer, G. Georgakos, J. Berthold, D. Schmitt-Landsiedel
{"title":"Dynamic state-retention flip flop for fine-grained sleep-transistor scheme","authors":"S. Henzler, Thomas Nirschi, C. Pacha, Peter Spindler, P. Teichmann, M. Fulde, J. Fischer, M. Eireiner, T. Fischer, G. Georgakos, J. Berthold, D. Schmitt-Landsiedel","doi":"10.1109/ESSCIR.2005.1541580","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541580","url":null,"abstract":"Fine-grained sleep transistor scheme is the rigorous application of power gating to reduce standby power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense amplifier based state retention flip-flop preserving the logical state of the circuit during this short idle times is proposed, that requires neither additional control signals nor an additional power supply for its state retention functionality and can be integrated into a standard design flow without any modifications. The trade-off between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100ps to 200ps.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130145277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 34GHz/1V prescaler in 90nm CMOS SOI 90nm CMOS SOI中的34GHz/1V预缩放器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541570
M. Sanduleanu, R. Ionita, A. Vladimirescu
{"title":"A 34GHz/1V prescaler in 90nm CMOS SOI","authors":"M. Sanduleanu, R. Ionita, A. Vladimirescu","doi":"10.1109/ESSCIR.2005.1541570","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541570","url":null,"abstract":"This paper presents a Ka band prescaler in a general-purpose 90nm SOI CMOS process (CMOS090/spl I.bar/SOI). Hereby, a D-latch concept is introduced. A stack inductor enhances its high frequency performance and reduces the sensitivity with process variations and temperature. The prescaler version with stack inductor has the minimum sensitivity at 31 GHz with an operation range of 13 to 34GHz. The prescaler without inductors has an operation range of 9 to 27GHz with minimum sensitivity at 23GHz. At 1MHz offset from the carrier, the phase noise of the divider amounts -127dBc/Hz. For on-wafer testing, the two versions of the prescaler were implemented in a 90nm SOI CMOS process (CMOS090/spl I.bar/SOI) with six metal layers and one thick top metal layer. The divider consumes 60mW from a 1V supply voltage and the active area is 350 /spl times/ 400/spl mu/m/sup 2/.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"82 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128743013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fully-integrated WCDMA SiGeC BiCMOS transceiver 全集成WCDMA SiGeC BiCMOS收发器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541674
B. Pellat, J. Blanc, F. Goussin, D. Thevenet, Sandrine Majcherczak, F. Reaute, D. Belot, P. Garcia, P. Persechini, Patrick Cerisier, P. Conti, P. Level, M. Kraemer, A. Granata
{"title":"Fully-integrated WCDMA SiGeC BiCMOS transceiver","authors":"B. Pellat, J. Blanc, F. Goussin, D. Thevenet, Sandrine Majcherczak, F. Reaute, D. Belot, P. Garcia, P. Persechini, Patrick Cerisier, P. Conti, P. Level, M. Kraemer, A. Granata","doi":"10.1109/ESSCIR.2005.1541674","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541674","url":null,"abstract":"This paper describes a WCDMA transceiver integrated and in a SiGe-C 0.25um BiCMOS process featuring Ft=60GHz bipolar transistor. The receiver part includes integrated zero-IF RF-Front-End. The transmitter is based on Variable IF architecture and includes a 64 dB gain control. All required PLL's and associated VCO's are also integrated. The receiver power consumption is 37mA (PLL included) and the transmitter consumes 60mA both under 2.7V power supply generated by an internal low drop regulator (LDO) directly connected to the battery voltage. Within the receive band, the receiver measurements shown 64dB of overall gain with a 5 dB NF DSB. The transmitter maximum output power is -3 dBm.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129766064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 3.33Gb/s (1200,720) low-density parity check code decoder 3.33Gb/s(1200,720)低密度奇偶校验码解码器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541597
Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee
{"title":"A 3.33Gb/s (1200,720) low-density parity check code decoder","authors":"Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ESSCIR.2005.1541597","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541597","url":null,"abstract":"In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm/sup 2/ 0.18/spl mu/m silicon area. The other 0.13/spl mu/m chip with the 10.24mm/sup 2/ core can further reach a 5.92Gb/s data rate under 1.02V supply.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128832103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A fast-hopping single-PLL 3-band UWB synthesizer in 0.25/spl mu/m SiGe BiCMOS 0.25/spl mu/m SiGe BiCMOS快速跳频单锁相环3波段超宽带合成器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541587
R. V. D. Beek, D. Leenaerts, G. V. D. Weide
{"title":"A fast-hopping single-PLL 3-band UWB synthesizer in 0.25/spl mu/m SiGe BiCMOS","authors":"R. V. D. Beek, D. Leenaerts, G. V. D. Weide","doi":"10.1109/ESSCIR.2005.1541587","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541587","url":null,"abstract":"A 0.44mm/sup 2/ fully-integrated 3-band MB-OFDM UWB synthesizer in a 0.25/spl mu/m SiGe BiCMOS process are presented. The single PLL, single SSB-mixer concept consumes 52mW from a 2.7V supply. Out-of-band spurious tones are below -50dBc, allowing cooperability with WLAN applications in the 2.4GHz and 5GHz range. The integrated phase noise is below 2 degrees rms. The measured hopping speed is well below the required 9.5ns.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125475903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信