90nm CMOS SOI中的34GHz/1V预缩放器

M. Sanduleanu, R. Ionita, A. Vladimirescu
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引用次数: 6

摘要

本文提出了一种基于通用90nm SOI CMOS工艺(CMOS090/spl .bar/SOI)的Ka波段预分频器。在此,引入了d锁存器的概念。堆叠电感提高了高频性能,降低了对工艺变化和温度的敏感性。带有堆叠电感的预量器版本在31 GHz时灵敏度最低,工作范围为13至34GHz。无电感的预分频器工作范围为9至27GHz,最小灵敏度为23GHz。在距离载波1MHz的偏移处,分频器的相位噪声为-127dBc/Hz。对于晶圆上测试,两个版本的预缩放器在90nm SOI CMOS工艺(CMOS090/spl I.bar/SOI)中实现,具有六个金属层和一个厚的顶部金属层。分压器在1V电源电压下消耗60mW,有效面积为350 /spl倍/ 400/spl亩/m/sup 2/。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 34GHz/1V prescaler in 90nm CMOS SOI
This paper presents a Ka band prescaler in a general-purpose 90nm SOI CMOS process (CMOS090/spl I.bar/SOI). Hereby, a D-latch concept is introduced. A stack inductor enhances its high frequency performance and reduces the sensitivity with process variations and temperature. The prescaler version with stack inductor has the minimum sensitivity at 31 GHz with an operation range of 13 to 34GHz. The prescaler without inductors has an operation range of 9 to 27GHz with minimum sensitivity at 23GHz. At 1MHz offset from the carrier, the phase noise of the divider amounts -127dBc/Hz. For on-wafer testing, the two versions of the prescaler were implemented in a 90nm SOI CMOS process (CMOS090/spl I.bar/SOI) with six metal layers and one thick top metal layer. The divider consumes 60mW from a 1V supply voltage and the active area is 350 /spl times/ 400/spl mu/m/sup 2/.
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