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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.最新文献

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The vector fixed point unit of the synergistic processor element of the cell architecture processor 单元结构处理器的协同处理器单元的向量定点单元
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2006-03-06 DOI: 10.1109/DATE.2006.243933
N. Mading, J. Leenstra, J. Pille, Rolf Sautter, S. Buttner, S. Ehrenreich, W. Haller
{"title":"The vector fixed point unit of the synergistic processor element of the cell architecture processor","authors":"N. Mading, J. Leenstra, J. Pille, Rolf Sautter, S. Buttner, S. Ehrenreich, W. Haller","doi":"10.1109/DATE.2006.243933","DOIUrl":"https://doi.org/10.1109/DATE.2006.243933","url":null,"abstract":"A vector fixed point unit (FXU) is designed to speed up multimedia processing. The FXU implements SIMD style integer arithmetic and permute operations. The adder, rotator and permute structure enables the use of static circuits only. The FXU was fabricated using IBM 90nm CMOS SOI technology.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123860369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Pushing CMOS beyond the roadmap 推动CMOS超越路线图
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546585
L. Risch
{"title":"Pushing CMOS beyond the roadmap","authors":"L. Risch","doi":"10.1109/ESSDER.2005.1546585","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546585","url":null,"abstract":"Today, the 90nm generation is in production and in spite of many roadblocks, the latest ITRS 04 expects that CMOS can be scaled down to the 22nm node and beyond. However, for conventional bulk CMOS serious challenges are evident and new transistors with better electrostatic channel control, lower off-currents and higher on-currents will be needed. Among them, multi-gate devices with very thin silicon channels are most promising. Several architectures like FinFET, wafer bonded double gate and SON gate all around have been demonstrated with good electrical characteristics at gate lengths of 25-10nm. Under certain assumptions for the SD regions, quantum mechanical simulations predict that silicon MOSFETs can be functional down to 2nm gate length. Multi-gate transistors have also been implemented in high density flash memory cells down to 20nm. Large Vt shifts suitable for multi-level storage were achieved. Therefore, it seems very realistic that the device roadmap will not end at the 22nm node. Assuming that manufacturing and cost issues can be fulfilled, CMOS will continue to dominate in the nanoelectronics era.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122311646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Analog/RF circuit design techniques for nanometerscale IC technologies 纳米级集成电路技术的模拟/射频电路设计技术
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSCIR.2005.1541556
B. Nauta, A. Annema
{"title":"Analog/RF circuit design techniques for nanometerscale IC technologies","authors":"B. Nauta, A. Annema","doi":"10.1109/ESSCIR.2005.1541556","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541556","url":null,"abstract":"CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130433335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Nanoelectronics: nanotubes, nanowires, molecules, and novel concepts 纳米电子学:纳米管、纳米线、分子和新概念
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-12 DOI: 10.1109/ESSDER.2005.1546583
H. Wong
{"title":"Nanoelectronics: nanotubes, nanowires, molecules, and novel concepts","authors":"H. Wong","doi":"10.1109/ESSDER.2005.1546583","DOIUrl":"https://doi.org/10.1109/ESSDER.2005.1546583","url":null,"abstract":"As device sizes approach the nanoscale, new opportunities arise from harnessing the physical and chemical properties at the nanoscale. Chemical synthesis, self-assembly, and templated self-assembly promise the precise fabrication of device structures or even the entire functional entity. Quantum phenomena and one- dimensional transport may lead to new functional devices with very different power/performance tradeoffs. New materials with novel electronic, optical, and mechanical properties emerge as a result of the ability to manipulate matter on a nanoscale. It is now feasible to contemplate new nanoelectronic systems based on new devices with completely new system architectures. This paper gives an overview of the materials, technology, and device opportunities in the nanoscale era. The focus of discussion is on nanotubes, nanowires, molecular devices, and novel device concepts for nanoelectronics.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125893919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and Bluetooth co-existence applications 一款低功耗高性能SiGe BiCMOS 802.11a/b/g收发器IC，适用于蜂窝和蓝牙共存应用
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541576
O. Charlon, M. Locher, H. Visser, D. Duperray, J. Cherr, M. Judson, A. Landesman, C. Hritz, U. Kohlschuetter, Yifeng Zhang, C. Ramesh, A. Daanen, M. Gao, S. Haas, V. Maheshwari, A. Bury, G. Nitsche, A. Wrzyszcz, W. Redman-White, H. Bonakdar, Rachid El Waffaoui, M. Bracey
{"title":"A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and Bluetooth co-existence applications","authors":"O. Charlon, M. Locher, H. Visser, D. Duperray, J. Cherr, M. Judson, A. Landesman, C. Hritz, U. Kohlschuetter, Yifeng Zhang, C. Ramesh, A. Daanen, M. Gao, S. Haas, V. Maheshwari, A. Bury, G. Nitsche, A. Wrzyszcz, W. Redman-White, H. Bonakdar, Rachid El Waffaoui, M. Bracey","doi":"10.1109/ESSCIR.2005.1541576","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541576","url":null,"abstract":"This paper describes a low-power, high-performance WLAN 802.11 a/b/g radio transceiver optimized for mobile applications and co-existence with on-board cellular and Bluetooth systems. The direct conversion architecture is optimized to achieve uncompromised RF performance at low power. A key transceiver requirement is a sensitivity of -77dBm (at the LNA input) in the presence of a GSM 1900 transmitter interferer while in 54Mb/s OFDM mode. The receiver chain achieves a NF of 2.8/3.2dB, consuming 168/185mW at 2.8V for the 2.4/5GHz bands respectively. Signal loopback and transmit power detection techniques are used in conjunction with the baseband modem processor to calibrate the transmitter LO leakage and the transceiver I/Q imbalances. Fabricated in a 70GHz f/sub T/ 0.25/spl mu/m SiGe BiCMOS technology for system-in-package (SiP) use, the dual-band, tri-mode transceiver occupies only 4.6mm/sup 2/.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123130524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications 一种10Mbit, 15gb /s带宽1T DRAM芯片，采用平面MOS存储电容，采用未经修改的150nm逻辑工艺，用于高密度片上存储器应用
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541633
D. Somasekhar, Shih-Lien Lu, B. Bloechel, G. Dermer, K. Lai, Sjeljar Borkar, V. De
{"title":"A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications","authors":"D. Somasekhar, Shih-Lien Lu, B. Bloechel, G. Dermer, K. Lai, Sjeljar Borkar, V. De","doi":"10.1109/ESSCIR.2005.1541633","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541633","url":null,"abstract":"A 10Mb planar 1T-IC DRAM chip is implemented in an unmodified 150nm micro-processor logic process. It achieves 15GBytes/sec bandwidth, 9.5nsec read access time with 197mW power at 1.5V, 110/spl deg/C. Worst-case refresh period is 100/spl mu/S at 110/spl deg/C with refresh power density of 0.18W/cm/sup 2/. Effective bit density of 42Mb/cm/sup 2/ is /spl sim/3/spl times/ better than the best 6T SRAM cache in the same technology.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121095927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An audio FIR-DAC in a BCD process for high power class-D amplifiers 用于高功率d类放大器的BCD过程中的音频FIR-DAC
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541659
T. Doorn, E. V. Tuijl, D. Schinkel, A. Annema, M. Berkhout, B. Nauta
{"title":"An audio FIR-DAC in a BCD process for high power class-D amplifiers","authors":"T. Doorn, E. V. Tuijl, D. Schinkel, A. Annema, M. Berkhout, B. Nauta","doi":"10.1109/ESSCIR.2005.1541659","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541659","url":null,"abstract":"A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at V/sub dd/ = 5 V and the chip area is 2 mm/sup 2/ including the reference diode that can be shared by more channels.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121357164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A low-frequency, sub 1.5-V micropower G/sub m/-C filter based on subthreshold MIFG MOS transistors 基于亚阈值MIFG MOS晶体管的低频、低于1.5 v的微功率G/sub m/ c滤波器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541627
A. E. Mourabit, G. Lu, P. Pittet
{"title":"A low-frequency, sub 1.5-V micropower G/sub m/-C filter based on subthreshold MIFG MOS transistors","authors":"A. E. Mourabit, G. Lu, P. Pittet","doi":"10.1109/ESSCIR.2005.1541627","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541627","url":null,"abstract":"We present a sub-1.5V and micropower filter with very low and tunable cut off frequency. It consists of low-G/sub m/ and wide-linear-range OTA using subthreshold MIFG (multiple input floating gate) MOS transistors. A linearization technique based on cancellation of cubic distortion term is implemented. The filter designed in a 0.8-/spl mu/m CMOS process can operate under a supply voltage V/sub dd/ as low as 1.2V. For V/sub dd/ = 1.5V, the filter has a linear range of 1.1 Vpp (with THD < 1%) and a tuning range from 0.5 to 200Hz, with power dissipation below 2/spl mu/W.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123790295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A fixed-point multimedia coprocessor with 50Mvertices/s programmable SIMD vertex shader for mobile applications 一个定点多媒体协处理器，具有50Mvertices/s可编程SIMD顶点着色器，用于移动应用程序
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541596
Ju-Ho Sohn, Jeong-Ho Woo, Ramchan Woo, H. Yoo
{"title":"A fixed-point multimedia coprocessor with 50Mvertices/s programmable SIMD vertex shader for mobile applications","authors":"Ju-Ho Sohn, Jeong-Ho Woo, Ramchan Woo, H. Yoo","doi":"10.1109/ESSCIR.2005.1541596","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541596","url":null,"abstract":"A fixed-point multimedia coprocessor is designed and integrated into an ARM-10 based mobile graphics processor for portable 2D and 3D multimedia applications. The user-programmable SIMD vertex shader with ARM-10 co-processor architecture realizes advanced 3D graphics algorithms and various multimedia functions. Different from conventional ARM coprocessor architecture, the multimedia coprocessor implements dual operations, by which parallel and streaming multimedia processing is enabled in mobile applications. For low power consumption, fixed-point SIMD datapath is designed with instruction-wise clock gating. The co-processor takes 10.2mm/sup 2/ in 0.18/spl mu/m 6-metal standard CMOS logic process and achieves 50Mvertices/s graphics performance with 75.4mW power consumption.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125445395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Single-chip CMOS pulse generator for UWB systems 用于超宽带系统的单片CMOS脉冲发生器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541612
Lydi Smaini, C. Tinella, D. Hélal, Claude Stoecklin, L. Chabert, Christophe Devaucelle, Régis Cattenoz, D. Belot
{"title":"Single-chip CMOS pulse generator for UWB systems","authors":"Lydi Smaini, C. Tinella, D. Hélal, Claude Stoecklin, L. Chabert, Christophe Devaucelle, Régis Cattenoz, D. Belot","doi":"10.1109/ESSCIR.2005.1541612","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541612","url":null,"abstract":"This paper describes the integration in a CMOS 130 nm technology of an ultra wide band (UWB) pulse generator. The implemented generator controls the output pulse shape, and thus the corresponding spectrum. Furthermore, the pulse generator supports both position modulation (2-PPM) and polarity modulation (BPSK) and draws 5 mA from 1.2 V. Spectral and temporal laboratory measurements of the single-chip pulse generator are presented.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116419160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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