用于高功率d类放大器的BCD过程中的音频FIR-DAC

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541659

T. Doorn, E. V. Tuijl, D. Schinkel, A. Annema, M. Berkhout, B. Nauta

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引用次数: 13

摘要

设计并实现了一种采用1位PWM输入信号的322系数半数字FIR-DAC，采用高压音频功率双极CMOS DMOS (BCD)工艺。这有利于BCD中模拟d类放大器的数字输入信号。FIR-DAC性能取决于该pwm信号的抗isi特性。由于脉冲响应具有抗死区和不匹配的特性，因此选择了只带正系数的脉冲响应。当DAC电流为0.5 mA时，动态范围为111 dB (a加权)，SINAD = 103 dB (a加权)。模拟部分的电流消耗为1mA，数字部分为4.8 mA。在V/sub / = 5 V时，功耗为29 mW，芯片面积为2 mm/sup /，包括可由更多通道共享的参考二极管。

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An audio FIR-DAC in a BCD process for high power class-D amplifiers

A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (A-weighted), with SINAD = 103 dB (A-weighted). The current consumption is 1mA for the analog part and 4.8 mA for the digital part. The power consumption is 29 mW at V/sub dd/ = 5 V and the chip area is 2 mm/sup 2/ including the reference diode that can be shared by more channels.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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