一种10Mbit, 15gb /s带宽1T DRAM芯片，采用平面MOS存储电容，采用未经修改的150nm逻辑工艺，用于高密度片上存储器应用

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541633

D. Somasekhar, Shih-Lien Lu, B. Bloechel, G. Dermer, K. Lai, Sjeljar Borkar, V. De

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引用次数: 7

摘要

采用未经修改的150nm微处理器逻辑工艺实现了10Mb平面1T-IC DRAM芯片。在1.5V, 110/spl度/C下，功率为197mW，带宽为15gb /s，读取时间为9.5nsec。最坏刷新周期为100/磅/亩/秒，刷新功率密度为0.18W/cm/sup 2/。有效位密度为42Mb/cm/sup / 2/是/spl / sim/3/spl倍/好于相同技术下最好的6T SRAM缓存。

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A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications

A 10Mb planar 1T-IC DRAM chip is implemented in an unmodified 150nm micro-processor logic process. It achieves 15GBytes/sec bandwidth, 9.5nsec read access time with 197mW power at 1.5V, 110/spl deg/C. Worst-case refresh period is 100/spl mu/S at 110/spl deg/C with refresh power density of 0.18W/cm/sup 2/. Effective bit density of 42Mb/cm/sup 2/ is /spl sim/3/spl times/ better than the best 6T SRAM cache in the same technology.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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