A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications

Abstract

A 10Mb planar 1T-IC DRAM chip is implemented in an unmodified 150nm micro-processor logic process. It achieves 15GBytes/sec bandwidth, 9.5nsec read access time with 197mW power at 1.5V, 110/spl deg/C. Worst-case refresh period is 100/spl mu/S at 110/spl deg/C with refresh power density of 0.18W/cm/sup 2/. Effective bit density of 42Mb/cm/sup 2/ is /spl sim/3/spl times/ better than the best 6T SRAM cache in the same technology.