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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.最新文献

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A modified LMS adaptive filter architecture with improved stability at RF 改进的LMS自适应滤波器结构，提高了射频稳定性
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541603
V. Aparin
{"title":"A modified LMS adaptive filter architecture with improved stability at RF","authors":"V. Aparin","doi":"10.1109/ESSCIR.2005.1541603","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541603","url":null,"abstract":"Stability of a conventional LMS adaptive filter at RF is analyzed using the Laplace transform. It is shown that the RF signal delays along the filter feedback loop can make it unstable. A simple modification to the filter architecture is proposed to improve the loop phase margin. A practical implementation of the proposed architecture in 0.25/spl mu/m CMOS technology is described. The designed filter is used as part of a cellular-band CDMA receiver to reject a transmitter signal leakage at the mixer input. It achieved the maximum rejection of 28dB.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123026526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.1% accuracy 100/spl Omega/-20M/spl Omega/ dynamic range integrated gas sensor interface circuit with 13+4 bit digital output 具有13+4位数字输出的0.1%精度100/spl Omega/-20M/spl Omega/动态范围集成气体传感器接口电路
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541632
M. Grassi, P. Malcovati, A. Baschirotto
{"title":"A 0.1% accuracy 100/spl Omega/-20M/spl Omega/ dynamic range integrated gas sensor interface circuit with 13+4 bit digital output","authors":"M. Grassi, P. Malcovati, A. Baschirotto","doi":"10.1109/ESSCIR.2005.1541632","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541632","url":null,"abstract":"This paper presents the design and the characterization of an integrated wide-range interface circuit for resistive sensors. The device is actually a multi-scale transresistance continuous time amplifier followed by a 13-bit incremental A/D converter. As shown in measurements the worst case resolution is near to 0.1% over a range of 5.3 decades [100/spl Omega/-20M/spl Omega/] thanks to a calibration technique which cancels offset and gain error mismatch between scales. The chip has been designed in 0.35/spl mu/m CMOS technology.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129752393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
An 18-GHz, 10.9-dBm fully-integrated power amplifier with 23.5% PAE in 130-nm CMOS 18ghz, 10.9 dbm全集成功率放大器，在130纳米CMOS中具有23.5%的PAE
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541578
C. Cao, H. Xu, Yu Su, K. O
{"title":"An 18-GHz, 10.9-dBm fully-integrated power amplifier with 23.5% PAE in 130-nm CMOS","authors":"C. Cao, H. Xu, Yu Su, K. O","doi":"10.1109/ESSCIR.2005.1541578","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541578","url":null,"abstract":"An 18-GHz fully integrated class-E power amplifier with 10.9-dBm saturated output power, and 23.5-% maximum PAE is fabricated in the UMC 130-nm digital CMOS process. At the saturated output, the required input power level is -5dBm and PA consumes 35mA from V/sub DD/=1.5V. The amplifier is single-ended and includes a 2-stage pre-amplifier and a driver stage. A mode-locking technique exploiting the instability of driver amplifier is used to improve the drive for the gate of output stage. The mode-locking improves PAE by /spl sim/3% and reduces the required input power level by /spl sim/6dB to get same output level.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123346431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Continuous-time DSPs, analog/digital computers and other mixed-domain circuits 连续时间dsp，模拟/数字计算机和其他混合域电路
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541571
Y. Tsividis, Glenn E. R. Cowan, Yee William Li, K. Shepard
{"title":"Continuous-time DSPs, analog/digital computers and other mixed-domain circuits","authors":"Y. Tsividis, Glenn E. R. Cowan, Yee William Li, K. Shepard","doi":"10.1109/ESSCIR.2005.1541571","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541571","url":null,"abstract":"This paper reviews our recent research, involving circuits and systems which mix domains traditionally kept separate. Several examples are given, including continuous-time digital signal processors and mixed analog/digital computers. It is argued that by mixing domains one can have advantages which would not otherwise be possible.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116504822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Improving DPA security by using globally-asynchronous locally-synchronous systems 通过使用全局异步本地同步系统提高DPA安全性
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541646
Frank K. Gürkaynak, S. Oetiker, H. Kaeslin, N. Felber, W. Fichtner
{"title":"Improving DPA security by using globally-asynchronous locally-synchronous systems","authors":"Frank K. Gürkaynak, S. Oetiker, H. Kaeslin, N. Felber, W. Fichtner","doi":"10.1109/ESSCIR.2005.1541646","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541646","url":null,"abstract":"Side channel analysis attacks, and particularly differential power analysis (DPA), pose a serious threat to cryptographic security. This is partly because the synchronous operation of traditional cipher hardware affords a fairly good correlation between the abstract power model used during analysis and the physical circuit under attack. As opposed to this, the globally-asynchronous locally-synchronous (GALS) AES cipher circuit discussed in this paper combines operation reordering and unpredictable latencies with three asynchronous clock domains and self-varying clock cycle times. Attackers are further confused by having functional units process random dummy data when idle. The design fabricated in a 0.25 /spl mu/m CMOS technology comprises 39,000 gate-equivalents, occupies approximately 1 mm/sup 2/ and achieves a peak throughput of more than 256 Mb/s.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124230802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A 10BIT 30MSPS CMOS A/D converter for high performance video applications 用于高性能视频应用的10BIT 30MSPS CMOS A/D转换器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541675
J. Li, Jianyun Zhang, Bo Shen, Xiao-Qing Zeng, Yawei Guo, T. Tang
{"title":"A 10BIT 30MSPS CMOS A/D converter for high performance video applications","authors":"J. Li, Jianyun Zhang, Bo Shen, Xiao-Qing Zeng, Yawei Guo, T. Tang","doi":"10.1109/ESSCIR.2005.1541675","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541675","url":null,"abstract":"This paper describes a 10bit 30 MSPS CMOS analog-to-digital converter (ADC) for high-speed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC adopts a power efficient amplifier sharing technique, an improved gate-bootstrapping technique for a wideband SHA, a proposed stable high-swing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25/spl mu/m CMOS technology show less than 0.4 least significant bit (LSB) and 0.85LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to 60MHz, which is the fourfold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 60 mW from a 3-V supply and occupies 1.36 mm/sup 2/.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127640906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Silicon bipolar circuits for wideband FM CATV transmission 宽带调频有线电视传输用硅双极电路
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541621
R. Rosales, M. K. Jackson
{"title":"Silicon bipolar circuits for wideband FM CATV transmission","authors":"R. Rosales, M. K. Jackson","doi":"10.1109/ESSCIR.2005.1541621","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541621","url":null,"abstract":"In optical transmission of analog multi-channel cable television, an alternative to lower the cost of system components is that of employing wideband frequency modulation. This approach requires wideband FM modulation circuits with GHz operation and demanding linear performance. In this paper we describe wideband FM modulator and demodulator circuits implemented in a 25GHz-ft silicon bipolar technology, that show for the first time 80-channel transmission attainable. Most notably, the use of emitter coupled multivibrator VCOs achieved record modulator linearity over a 1.5-2.5GHz frequency range, and proved to outperform in linearity and noise the best wideband optoelectronic modulators. The demodulator response is linear over the range from 1-3.5GHz. Modulator phase noise is -122.5dBc/Hz @ 50MHz, and was found to be improvable through a novel phase noise reduction technique.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115787914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28.5 GHz monolithic cascode LNA with 70GHz f/sub T/ SiGe HBTs 28.5 GHz单片级联LNA, 70GHz f/sub T/ SiGe hbt
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541566
F. Fortes, J. C. Freire, D. Leenaerts, R. Mahmoudi, A. Roermund
{"title":"A 28.5 GHz monolithic cascode LNA with 70GHz f/sub T/ SiGe HBTs","authors":"F. Fortes, J. C. Freire, D. Leenaerts, R. Mahmoudi, A. Roermund","doi":"10.1109/ESSCIR.2005.1541566","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541566","url":null,"abstract":"This paper presents the design and experimental results of a monolithic cascode LNA for 28.5GHz applications using SiGe HBTs. It shows that designing circuits at frequencies beyond f/sub T//3 is possible. The best experimental results are obtained at 26GHz with a 3.3V supply voltage: |S/sub 21/| = 10.4dB, input and output matching better than -10dB. The measured noise figure is 6.4dB.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114819087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 1.2V-21dBm OIP3 4/sup th/-order active-g/sub m/-RC reconfigurable (UMTS/WLAN) filter with on-chip tuning designed with an automatic tool 一个1.2V-21dBm oip3.4 /sup /-order active-g/sub - m/-RC可重构(UMTS/WLAN)滤波器，带有片上调谐，采用自动工具设计
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541623
S. D’Amico, V. Giannini, A. Baschirotto
{"title":"A 1.2V-21dBm OIP3 4/sup th/-order active-g/sub m/-RC reconfigurable (UMTS/WLAN) filter with on-chip tuning designed with an automatic tool","authors":"S. D’Amico, V. Giannini, A. Baschirotto","doi":"10.1109/ESSCIR.2005.1541623","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541623","url":null,"abstract":"A 4/sup th/ order low-pass continuous-time filter for a UMTS/WLAN receiver of a reconfigurable terminal is presented. The filter uses two active-g/sub m/-RC biquad cells, where a single opamp is used for two poles and its unity-gain-bandwidth is comparable to the filter cut-off frequency. Thus, the opamp power consumption is strongly reduced with other closed-loop filter configuration. The cut-off frequency deviation due to the technological spread, aging and temperature variation is adjusted by an on-chip tuning circuit. The device in a 0.13/spl mu/m CMOS technology occupies a 0.9mm/sup 2/ area and consumes 3.4mW and 14.2mW for the UMTS and WLAN, respectively. The full chip has been designed using an automatic design tool and the experimental results agree with the expected performance.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114856464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 100 /spl mu/W, 1.9GHz oscillator with fully digital frequency tuning 100 /spl mu/W, 1.9GHz振荡器，全数字频率调谐
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541641
Nathan Pletcher, J. Rabaey
{"title":"A 100 /spl mu/W, 1.9GHz oscillator with fully digital frequency tuning","authors":"Nathan Pletcher, J. Rabaey","doi":"10.1109/ESSCIR.2005.1541641","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541641","url":null,"abstract":"A 1.9GHz CMOS digitally controlled oscillator (DCO) is designed in a standard 0.13/spl mu/m process, targeting ultra low power frequency synthesizers for wireless sensor network transceivers. The oscillator exploits subthreshold device operation and a low 0.5V supply to achieve power consumption of only 100/spl mu/W. A novel switched capacitor configuration is employed to realize a frequency resolution of 200 kHz with a tuning range of 150MHz. High quality bondwire inductors also reduce power consumption. The phase noise is -114dBc/Hz at 1MHz offset, achieving performance competitive with other published work.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127206733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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