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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.最新文献

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A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors 用于CMOS图像传感器的具有像素噪声和列方向偏移抵消的循环A/D转换器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541647
M. Furuta, S. Kawahito, Toru Inoue, Y. Nishikawa
{"title":"A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors","authors":"M. Furuta, S. Kawahito, Toru Inoue, Y. Nishikawa","doi":"10.1109/ESSCIR.2005.1541647","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541647","url":null,"abstract":"A cyclic analog-to-digital converter (ADC) with pixel noise and column-wise offset canceling for CMOS image sensors is presented. By adding cross connection switches to a cyclic ADC, a column-wise fixed pattern noise due to the amplifier's offset variations is greatly reduced. The proposed ADC also acts as a pixel noise canceller The ADC is optimized with respect to area and power consumption in order to allow the integration of a parallel array at the column of the image sensors. A prototype 12-bit cyclic ADC implemented using a 0.25 /spl mu/m CMOS technology exhibits a 4LSB maximum integral nonlinearity (INL) and 0.9LSB maximum differential non-linearity (DNL) without calibration and 1.5mVp-p column-wise offset deviation. The ADC has 62dB signal-to-noise ratio at 1 Msample/s. The power dissipation is 0.43mW at 3.3V supplies, and the area of one channel is 0.04 /spl times/ 1.2mm/sup 2/.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129927656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components 使用CMOS fpga和PECL元件实现多千兆赫测试系统
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541617
D. Keezer, C. Gray, A. Majid, N. Taher
{"title":"Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components","authors":"D. Keezer, C. Gray, A. Majid, N. Taher","doi":"10.1109/ESSCIR.2005.1541617","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541617","url":null,"abstract":"Two research projects are described that develop low-cost techniques for testing multi-gigahertz devices. Each project uses commercially available components to keep costs low, and achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. An FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized emitter-coupled logic achieves multi-gigahertz data rates with about /spl plusmn/25ps timing accuracy. This paper has been adapted from (Keezer, 2005).","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129091725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A BiCMOS ultrasound front end signal processor for high temperature applications 用于高温应用的BiCMOS超声前端信号处理器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541616
O. Vermesan, L. Blystad, R. Bahr, M. Hjelstuen, L. Beneteau, B. Froelich
{"title":"A BiCMOS ultrasound front end signal processor for high temperature applications","authors":"O. Vermesan, L. Blystad, R. Bahr, M. Hjelstuen, L. Beneteau, B. Froelich","doi":"10.1109/ESSCIR.2005.1541616","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541616","url":null,"abstract":"A mixed signal ASIC that implements an ultrasound front end receiver in a 0.6/spl mu/m BiCMOS HotASIC/spl reg/ technology is described. The ASIC includes a low noise amplifier (LNA), a programmable gain amplifier (PGA), an output differential amplifier (ODA), a second order sigma delta modulator (SDM) and is the most compact system for high temperature ultrasound applications reported in literature. The circuit has a programmable gain and is designed for measuring the signal response (200kHz to 700kHz) from an ultrasound transducer. At 48MHz clock frequency and 200/spl deg/C the power consumption is 85mW from a single 5V supply. The die area of the chip is 5.52 mm/sup 2/.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116059275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel four-quadrant analog multiplier using SOI four-gate transistors (G/sup 4/-FETs) 基于SOI四栅极晶体管(G/sup 4/- fet)的新型四象限模拟乘法器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541669
K. Akarvardar, Suheng Chen, B. Blalock, S. Cristoloveanu, P. Gentil, M. Mojarradi
{"title":"A novel four-quadrant analog multiplier using SOI four-gate transistors (G/sup 4/-FETs)","authors":"K. Akarvardar, Suheng Chen, B. Blalock, S. Cristoloveanu, P. Gentil, M. Mojarradi","doi":"10.1109/ESSCIR.2005.1541669","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541669","url":null,"abstract":"A novel analog multiplier using SOI four-gate transistors (G/sup 4/-FETs) is presented. Thanks to the multiple inputs of the G/sup 4/-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers. Only four G/sup 4/-FETs are needed to build the multiplier core. The circuit is feasible with a standard SOI CMOS process. Two different configurations, both based on the linear modulation of the front-gate threshold voltage by the junction-gates, are presented. This paper addresses the theoretical analysis as well as the preliminary measurement results.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125108728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Electrical measurement of alignment for 3D stacked chips 三维堆叠芯片对准的电气测量
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541631
R. Canegallo, Mauro Mirandola, A. Fazzi, L. Magagni, R. Guerrieri, K. Kaschlun
{"title":"Electrical measurement of alignment for 3D stacked chips","authors":"R. Canegallo, Mauro Mirandola, A. Fazzi, L. Magagni, R. Guerrieri, K. Kaschlun","doi":"10.1109/ESSCIR.2005.1541631","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541631","url":null,"abstract":"This paper presents an electronic system based on integrated CMOS capacitive sensors that enables to determine the alignment between two chips assembled in a three-dimensional (3D) stacking configuration. Two different interface circuits are described for the on-chip measurement of alignment along vertical Z-axis and lateral X/Y-axis. A test chip has been fabricated in 0.13/spl mu/m, 6 metal standard CMOS process to test the multi-axis alignment system based on 3D sensors. A capacitive charge variation of 1 fF over 15fF corresponding to a resolution accuracy of 0.5/spl mu/m over a range of 50/spl mu/m has been measured. Sensors are 120/spl mu/m /spl times/ 30/spl mu/m and power consumption is 200/spl mu/W.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133016813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
SOI four-gate transistors (G/sup 4/-FETs) for high voltage analog applications 用于高压模拟应用的SOI四栅极晶体管(G/sup 4/- fet)
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541622
Suheng Chen, J. Vandersand, B. Blalock, K. Akarvardar, S. Cristoloveanu, M. Mojarradi
{"title":"SOI four-gate transistors (G/sup 4/-FETs) for high voltage analog applications","authors":"Suheng Chen, J. Vandersand, B. Blalock, K. Akarvardar, S. Cristoloveanu, M. Mojarradi","doi":"10.1109/ESSCIR.2005.1541622","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541622","url":null,"abstract":"A new approach for high-voltage analog applications that utilizes SOI four-gate transistors (G/sup 4/-FETs) is presented. The proposed solution achieves high-voltage operation (10 V and higher) with no additional cost of fabrication (compatible with standard SOI) and minimal added design overhead compared to their MOSFET counterparts. Measurement results of high-voltage current mirrors and differential pairs show superior HV capability with small signal performance comparable to their MOSFET counterparts. By using the high-voltage current mirror and differential pair as basic building blocks, a differential amplifier is built and tested with a 20 V supply.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133022448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Phase noise analysis and design of a 3-GHz bipolar differential colpitts VCO 3ghz双极差动压控振荡器的相位噪声分析与设计
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541642
Xiaoyan Wang, A. Fard, P. Andreani
{"title":"Phase noise analysis and design of a 3-GHz bipolar differential colpitts VCO","authors":"Xiaoyan Wang, A. Fard, P. Andreani","doi":"10.1109/ESSCIR.2005.1541642","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541642","url":null,"abstract":"This paper presents a low-phase-noise differential bipolar Colpitts VCO, implemented in a 0.35/spl mu/m BiCMOS process. A time-variant phase noise analysis yields closed- form symbolic expressions for the dominant noise sources in the 1/f/sup 2/ phase-noise region. Measurements show a phase noise of -123 dBc/Hz at 1MHz offset from a 2.8-3.1 GHz carrier, for a figure-of-merit of 183 dBc/Hz. A very good agreement between the derived theoretical formulas, spectreRF simulations, and measurements is observed.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134087710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
All CMOS low power platform for dielectrophoresis bio-analysis 全CMOS低功耗介电泳生物分析平台
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541629
A. Enteshari, G. Jullien, O. Yadid-Pecht, K. Kaler
{"title":"All CMOS low power platform for dielectrophoresis bio-analysis","authors":"A. Enteshari, G. Jullien, O. Yadid-Pecht, K. Kaler","doi":"10.1109/ESSCIR.2005.1541629","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541629","url":null,"abstract":"In this paper, we present a new architecture for dielectrophoresis (DEP) analysis with programmable planar arrays of micro-electrodes called Lexel/spl trade/. This software configurable architecture is able to implement a variety of AC electrokinetic techniques. The architecture is developed as a flexible IP (intellectual property) block and in conjunction with integrated microfluidic devices and other third-party IP blocks, form the analysis function in a low power system-on-chip bio-analysis platform. This design is basically a two dimensional randomly addressable electrode array with the feature of being able to be driven by one of four sinusoidal analog signals. To reduce the electrode size, we introduce the \"super-electrode\", which requires less periphery circuitry. The Lexel/spl trade/ array and supporting circuitry are designed on a single chip using a standard 0.18/spl mu/m CMOS process.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124856931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fast AFC technique using a code estimation and binary search algorithm for wideband frequency synthesis 快速AFC技术采用码估计和二叉搜索算法进行宽带频率合成
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541589
Kun-Seok Lee, Eun-yung Sung, In-Chul Hwang, Byeong-ha Park
{"title":"Fast AFC technique using a code estimation and binary search algorithm for wideband frequency synthesis","authors":"Kun-Seok Lee, Eun-yung Sung, In-Chul Hwang, Byeong-ha Park","doi":"10.1109/ESSCIR.2005.1541589","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541589","url":null,"abstract":"This paper presents some skills to improve locking property in wideband frequency synthesizers. To support a wide frequency range with a single on-chip voltage controlled oscillator (VCO) without deteriorating lock time, we introduce an adaptive frequency calibration (AFC) technique, which is using a code estimation and binary search algorithm to reduce the number of comparisons in AFC mode. In addition, by varying the threshold frequency, which is a criterion to discriminate one AFC code from others, in accordance with the requested VCO output frequency, the unnecessary transition time can be reduced during phase-locked loop (PLL) settling mode. A fractional-N frequency synthesizer with an on-chip LC VCO was implemented in 0.18-/spl mu/m CMOS technology to verify the performance. The measurement results showed less than 35-/spl mu/s AFC time with 5-bit AFC, and total lock time was found to be less than 65-/spl mu/s with 30 KHz PLL loop bandwidth. The frequency range was more than 400 MHz.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123528186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Antenna and input stages of a 470-710 MHz silicon TV tuner for portable applications 用于便携式应用的470-710 MHz硅电视调谐器的天线和输入级
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541604
V. Rambeau, H. Brekelmans, M. Notten, K. Boyle, J. V. Sinderen
{"title":"Antenna and input stages of a 470-710 MHz silicon TV tuner for portable applications","authors":"V. Rambeau, H. Brekelmans, M. Notten, K. Boyle, J. V. Sinderen","doi":"10.1109/ESSCIR.2005.1541604","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541604","url":null,"abstract":"This paper describes the antenna and input stages of a silicon TV-tuner intended for portable devices such as cell phones, laptops and PDAs. The tuner meets the requirements of the mobile and portable DVB-T radio access interface specifications MBRAI. The first stages of the tuner comprise a broadband antenna, a matching and filtering circuit, and LNA. The frequency band of operation is 470-710MHz (DVB-H). The matching and filtering circuitry comprises a strong GSM trap that attenuates the GSM frequencies by more than 40dB. The overall power gain is 20 /spl plusmn/ 3dB in the band, and the NF of the total chain is less than 4dB. The power consumption is 21mW from 2.5V supply. The LNA is fabricated in a 0.25/spl mu/m, 35GHz f/sub T/ BiCMOS technology based on D. Szmyd et al. (2001).","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122581768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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