A novel four-quadrant analog multiplier using SOI four-gate transistors (G/sup 4/-FETs)

Abstract

A novel analog multiplier using SOI four-gate transistors (G/sup 4/-FETs) is presented. Thanks to the multiple inputs of the G/sup 4/-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers. Only four G/sup 4/-FETs are needed to build the multiplier core. The circuit is feasible with a standard SOI CMOS process. Two different configurations, both based on the linear modulation of the front-gate threshold voltage by the junction-gates, are presented. This paper addresses the theoretical analysis as well as the preliminary measurement results.