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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.最新文献

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24 GHz LNA in 90nm RF-CMOS with high-Q above-IC inductors 采用高q ic以上电感器的90nm RF-CMOS中的24 GHz LNA
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541565
O. Dupuis, Xiao Sun, G. Carchon, P. Soussan, M. Ferndahl, S. Decoutere, W. Raedt
{"title":"24 GHz LNA in 90nm RF-CMOS with high-Q above-IC inductors","authors":"O. Dupuis, Xiao Sun, G. Carchon, P. Soussan, M. Ferndahl, S. Decoutere, W. Raedt","doi":"10.1109/ESSCIR.2005.1541565","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541565","url":null,"abstract":"K-band RF capabilities of 90nm RF-CMOS combined with thin-film above-IC high-Q inductors is assessed by means of a 24 GHz LNA. The LNA, implemented as a single stage common-source amplifier led to state-of-the art results for CMOS technology at 24 GHz. Record noise figure of 3.2 dB is obtained with a gain of 7.5 dB. Input and output matching are respectively -16 dB and -30 dB. The LNA works with a 1V supply voltage and consumes only 10.6 mA.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123913926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Memory testing improvements through different stress conditions 不同压力条件下记忆测试的改善
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541619
A. Majhi, M. Azimane, G. Gronthoud, M. Lousberg, S. Eichenberger, Fred Bowen
{"title":"Memory testing improvements through different stress conditions","authors":"A. Majhi, M. Azimane, G. Gronthoud, M. Lousberg, S. Eichenberger, Fred Bowen","doi":"10.1109/ESSCIR.2005.1541619","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541619","url":null,"abstract":"This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products. The above test conditions have been validated to screen out the bad chips on real silicon (on a test-chip) built on CMOS 0.18 /spl mu/m technology.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124750371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A clock-less low-voltage AES crypto-processor 无时钟低压AES密码处理器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541645
G. Bouesse, M. Renaudin, A. Witon, F. Germain
{"title":"A clock-less low-voltage AES crypto-processor","authors":"G. Bouesse, M. Renaudin, A. Witon, F. Germain","doi":"10.1109/ESSCIR.2005.1541645","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541645","url":null,"abstract":"This paper presents a concrete evaluation of quasi delay insensitive (QDI) asynchronous logic in terms of current consumption within a wide range of supply voltages. The designed and fabricated circuit is a QDI advanced encryption standard (AES) crypto-processor, compliant with the NIST standard FIPS197. This circuit exploits fundamental properties of the QDI asynchronous logic, especially delay insensitivity, to enable relaxed operating conditions. The circuit, powered at 1.2 volt, ciphers a 128 bit data using a 128 bit key in 910 ns which corresponds to a ciphering rate of 141 Mbits per second. Due to the robustness of the clock-less QDI logic, the circuit is functional within a wide voltage range, down to 0.4 Volt. With such a low supply voltage the chip consumes 200 /spl mu/A sustaining a ciphering data rate of 6.4 Mbits/s. Moreover, clock-less circuits also generate less electromagnetic noise. This work demonstrates that QDI asynchronous logic is particularly interesting in secure, low-voltage, low-power and low-noise applications. These properties are clearly suitable to address different markets such as smartcard and mobile phones.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123059620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A precision high voltage wave-shaper for multi-Gbit source side injection MLC NOR flash memory 用于多gb源侧注入MLC NOR闪存的高精度高压整形器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541636
H. Tran, William John Saiki, J. Frayer, Thuan Vu, A. Ly, S. Nguyen, Hung Quoc Nguyen, D. J. Lee, M. Briner
{"title":"A precision high voltage wave-shaper for multi-Gbit source side injection MLC NOR flash memory","authors":"H. Tran, William John Saiki, J. Frayer, Thuan Vu, A. Ly, S. Nguyen, Hung Quoc Nguyen, D. J. Lee, M. Briner","doi":"10.1109/ESSCIR.2005.1541636","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541636","url":null,"abstract":"A precision high voltage wave-shaper is demonstrated in 0.18/spl mu/m 64-256Meg NOR SSI flash MLC memory chip to demonstrate feasibility of a /spl sim/8bit accuracy HV delivering system for 1.8V multi giga bit (>4 Gbit) density 4bits/cell multilevel memory. Dynamic adaptive HV bias scheme (DYAHV) and unique nested array driving loop shown for the first time in this work.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121443082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.6V 100dB 5.2MHz transconductance amplifier realized in a multi-V/sub T/ process 以多v /sub /工艺实现的0.6V 100dB 5.2MHz跨导放大器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541606
A. Bargagli-Stoffi, J. Sauerbrey, R. Thewes, D. Schmitt-Landsiedel
{"title":"A 0.6V 100dB 5.2MHz transconductance amplifier realized in a multi-V/sub T/ process","authors":"A. Bargagli-Stoffi, J. Sauerbrey, R. Thewes, D. Schmitt-Landsiedel","doi":"10.1109/ESSCIR.2005.1541606","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541606","url":null,"abstract":"A fully differential transconductance amplifier (OTA) realized in a standard 0.12/spl mu/m multi-V/sub T/ CMOS process is presented. Its class AB output stage is able to drive large capacitive loads with rail-to-rail signal swing. At 0.6V supply voltage, measured low frequency gain and gain bandwidth product exceed 100dB and 5.2MHz, respectively. Proper operation is achieved for supply voltages between 0.5V and 0.9V.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121568284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5.1-/spl mu/W UHF RFID tag chip integrated with sensors for wireless environmental monitoring 一个5.1-/spl mu/W的超高频RFID标签芯片，集成传感器，用于无线环境监测
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541614
Namjun Cho, Seong-Jun Song, Sunyoung Kim, Shiho Kim, H. Yoo
{"title":"A 5.1-/spl mu/W UHF RFID tag chip integrated with sensors for wireless environmental monitoring","authors":"Namjun Cho, Seong-Jun Song, Sunyoung Kim, Shiho Kim, H. Yoo","doi":"10.1109/ESSCIR.2005.1541614","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541614","url":null,"abstract":"An RF-powered transponder with temperature and photo sensors is designed and fabricated for environmental monitoring. The transponder gathers power from external ISM (860-960MHz) band RF signal and senses ambient temperature and light. It contains a supply voltage generator, a temperature-compensated ring oscillator, an oversampling synchronizer, a PTAT temperature sensor and an abrupt transition buffered photo sensor. Its internal clock frequency has variation less than 7% for 1.5-V supply voltage and 90/spl deg/C temperature change. The transponder occupies 0.4mm/sup 2/ with 0.25-/spl mu/m CMOS process and dissipates only 5.14-/spl mu/W during active state.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"380 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116056005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 184
A 1.2V CMOS multiplier for 10 Gbit/s equalization 1.2V CMOS乘法器，可实现10gbit /s均衡
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541639
Justin P. Abbott, C. Plett, J. Rogers
{"title":"A 1.2V CMOS multiplier for 10 Gbit/s equalization","authors":"Justin P. Abbott, C. Plett, J. Rogers","doi":"10.1109/ESSCIR.2005.1541639","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541639","url":null,"abstract":"This paper describes the design of a low power 1.2V CMOS multiplier for a 10 Gbit/s continuous time FIR filter. The multiplier can be digitally controlled without the use of a Digital to Analog Converter and has 32 possible gain settings from -1 to + 1. To achieve negative gain an inverting switch is used at the input of the multiplier, reducing loading at the summing node by 50%. As the bandwidth bottle neck occurs at the summing node, this allows for higher frequency operation or an increase in the number of multipliers per summing node. The gain errors are less than 2%, linearity errors are less than 3.3%, and the power consumption is 1.5mW.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117088487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 10mW 81dB cascaded multibit quadrature /spl Sigma//spl Delta/ ADC with a dynamic element matching scheme 一个10mW 81dB级联多位正交/spl Sigma//spl Delta/ ADC，采用动态元件匹配方案
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541657
R. Maurino, C. Papavassiliou
{"title":"A 10mW 81dB cascaded multibit quadrature /spl Sigma//spl Delta/ ADC with a dynamic element matching scheme","authors":"R. Maurino, C. Papavassiliou","doi":"10.1109/ESSCIR.2005.1541657","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541657","url":null,"abstract":"A multibit 2-0 cascaded quadrature /spl Sigma//spl Delta/ modulator is presented which attains 81 dB dynamic range in a 200kHz bandwidth at an IF of 10MHz. A simple dynamic element matching (DEM) scheme minimizes the mirror in-band aliases caused by mismatch between the I and Q channel. The integral nonlinearity (INL) errors from the multibit feedback DAC are noise-shaped by a quadrature variant of the data weighted averaging algorithm (DWA). Clocked at 13.1 MHz, the ADC consumes 10mW from a 2.1 V supply.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"483 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116062379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A novel 40-GHz flip-flop-based frequency divider in 0.18/spl mu/m CMOS 基于0.18/spl mu/m CMOS的新型40 ghz触发器分频器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541590
R. Mohanavelu, P. Heydari
{"title":"A novel 40-GHz flip-flop-based frequency divider in 0.18/spl mu/m CMOS","authors":"R. Mohanavelu, P. Heydari","doi":"10.1109/ESSCIR.2005.1541590","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541590","url":null,"abstract":"This paper presents a 40GHz flip-flop-based frequency divider incorporating a latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode, to speed up the latch operation and to increase the driving capability. The proposed frequency divider performs at 40GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18/spl mu/m SiGe BiCMOS process provided by Jazz Semiconductor, where only CMOS transistors were used. It draws 5mA current from a 1.8V supply voltage.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116077773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits 一种采用浮门mos低功耗多数投票电路的高速中值滤波VLSI
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541575
H. Yamasaki, T. Shibata
{"title":"A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits","authors":"H. Yamasaki, T. Shibata","doi":"10.1109/ESSCIR.2005.1541575","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541575","url":null,"abstract":"A low-power and high-speed mixed-signal VLSI median filter has been developed. The binary search algorithm has been employed and the median filter circuit was built using majority voting circuits. As a result, small latency median search has been established. In order to achieve a low power operation, majority voting circuits of voltage mode of operation have been developed based on the floating gate MOS technology. An 8-b 41-input median filter circuit was designed and fabricated in 0.35-/spl mu/m 2-poly 3-metal CMOS technology as a proof-of-concept chip and the operation was experimentally demonstrated. It was shown that more than 70% power reduction has been achieved as compared to our previous work presented in M. Yagi et al. (2003) employing current-mode MVCs, while preserving the high-speed performance achieved in the work.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129300807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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