A 1.2V CMOS multiplier for 10 Gbit/s equalization

Abstract

This paper describes the design of a low power 1.2V CMOS multiplier for a 10 Gbit/s continuous time FIR filter. The multiplier can be digitally controlled without the use of a Digital to Analog Converter and has 32 possible gain settings from -1 to + 1. To achieve negative gain an inverting switch is used at the input of the multiplier, reducing loading at the summing node by 50%. As the bandwidth bottle neck occurs at the summing node, this allows for higher frequency operation or an increase in the number of multipliers per summing node. The gain errors are less than 2%, linearity errors are less than 3.3%, and the power consumption is 1.5mW.