H. Tran, William John Saiki, J. Frayer, Thuan Vu, A. Ly, S. Nguyen, Hung Quoc Nguyen, D. J. Lee, M. Briner
{"title":"用于多gb源侧注入MLC NOR闪存的高精度高压整形器","authors":"H. Tran, William John Saiki, J. Frayer, Thuan Vu, A. Ly, S. Nguyen, Hung Quoc Nguyen, D. J. Lee, M. Briner","doi":"10.1109/ESSCIR.2005.1541636","DOIUrl":null,"url":null,"abstract":"A precision high voltage wave-shaper is demonstrated in 0.18/spl mu/m 64-256Meg NOR SSI flash MLC memory chip to demonstrate feasibility of a /spl sim/8bit accuracy HV delivering system for 1.8V multi giga bit (>4 Gbit) density 4bits/cell multilevel memory. Dynamic adaptive HV bias scheme (DYAHV) and unique nested array driving loop shown for the first time in this work.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A precision high voltage wave-shaper for multi-Gbit source side injection MLC NOR flash memory\",\"authors\":\"H. Tran, William John Saiki, J. Frayer, Thuan Vu, A. Ly, S. Nguyen, Hung Quoc Nguyen, D. J. Lee, M. Briner\",\"doi\":\"10.1109/ESSCIR.2005.1541636\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A precision high voltage wave-shaper is demonstrated in 0.18/spl mu/m 64-256Meg NOR SSI flash MLC memory chip to demonstrate feasibility of a /spl sim/8bit accuracy HV delivering system for 1.8V multi giga bit (>4 Gbit) density 4bits/cell multilevel memory. Dynamic adaptive HV bias scheme (DYAHV) and unique nested array driving loop shown for the first time in this work.\",\"PeriodicalId\":239980,\"journal\":{\"name\":\"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2005.1541636\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2005.1541636","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
在0.18/spl mu/m 64-256Meg NOR SSI闪存芯片上演示了一种高精度高压整形器,以验证1.8V多千兆比特(>4 Gbit)密度4bits/cell多电平存储器中/spl sim/8bit精度高压传输系统的可行性。本文首次提出了动态自适应高压偏置方案(DYAHV)和独特的嵌套阵列驱动回路。
A precision high voltage wave-shaper for multi-Gbit source side injection MLC NOR flash memory
A precision high voltage wave-shaper is demonstrated in 0.18/spl mu/m 64-256Meg NOR SSI flash MLC memory chip to demonstrate feasibility of a /spl sim/8bit accuracy HV delivering system for 1.8V multi giga bit (>4 Gbit) density 4bits/cell multilevel memory. Dynamic adaptive HV bias scheme (DYAHV) and unique nested array driving loop shown for the first time in this work.