不同压力条件下记忆测试的改善

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541619

A. Majhi, M. Azimane, G. Gronthoud, M. Lousberg, S. Eichenberger, Fred Bowen

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引用次数: 1

摘要

本文介绍了工业环境下各种应力条件(主要是电压和频率)对深亚微米嵌入式存储器中电阻性短路和开放缺陷检测的有效性。对极低电压、高压和高速试验的仿真研究表明，高质量产品需要应力条件。上述测试条件已经过验证，可以在基于CMOS 0.18 /spl mu/m技术的实际硅(在测试芯片上)上筛选出不良芯片。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Memory testing improvements through different stress conditions

This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products. The above test conditions have been validated to screen out the bad chips on real silicon (on a test-chip) built on CMOS 0.18 /spl mu/m technology.

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来源期刊

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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