Memory testing improvements through different stress conditions

Abstract

This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products. The above test conditions have been validated to screen out the bad chips on real silicon (on a test-chip) built on CMOS 0.18 /spl mu/m technology.