一个10mW 81dB级联多位正交/spl Sigma//spl Delta/ ADC，采用动态元件匹配方案

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541657

R. Maurino, C. Papavassiliou

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引用次数: 4

摘要

提出了一种多比特2-0级联正交/spl Sigma//spl Delta/调制器，该调制器在200kHz带宽下，在10MHz中频下可实现81 dB的动态范围。一个简单的动态元素匹配(DEM)方案最大限度地减少了由I和Q通道不匹配引起的镜像带内别名。多比特反馈DAC的积分非线性(INL)误差通过数据加权平均算法(DWA)的正交变体进行噪声整形。时钟为13.1 MHz, ADC从2.1 V电源消耗10mW。

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A 10mW 81dB cascaded multibit quadrature /spl Sigma//spl Delta/ ADC with a dynamic element matching scheme

A multibit 2-0 cascaded quadrature /spl Sigma//spl Delta/ modulator is presented which attains 81 dB dynamic range in a 200kHz bandwidth at an IF of 10MHz. A simple dynamic element matching (DEM) scheme minimizes the mirror in-band aliases caused by mismatch between the I and Q channel. The integral nonlinearity (INL) errors from the multibit feedback DAC are noise-shaped by a quadrature variant of the data weighted averaging algorithm (DWA). Clocked at 13.1 MHz, the ADC consumes 10mW from a 2.1 V supply.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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