O. Vermesan, L. Blystad, R. Bahr, M. Hjelstuen, L. Beneteau, B. Froelich
{"title":"用于高温应用的BiCMOS超声前端信号处理器","authors":"O. Vermesan, L. Blystad, R. Bahr, M. Hjelstuen, L. Beneteau, B. Froelich","doi":"10.1109/ESSCIR.2005.1541616","DOIUrl":null,"url":null,"abstract":"A mixed signal ASIC that implements an ultrasound front end receiver in a 0.6/spl mu/m BiCMOS HotASIC/spl reg/ technology is described. The ASIC includes a low noise amplifier (LNA), a programmable gain amplifier (PGA), an output differential amplifier (ODA), a second order sigma delta modulator (SDM) and is the most compact system for high temperature ultrasound applications reported in literature. The circuit has a programmable gain and is designed for measuring the signal response (200kHz to 700kHz) from an ultrasound transducer. At 48MHz clock frequency and 200/spl deg/C the power consumption is 85mW from a single 5V supply. The die area of the chip is 5.52 mm/sup 2/.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A BiCMOS ultrasound front end signal processor for high temperature applications\",\"authors\":\"O. Vermesan, L. Blystad, R. Bahr, M. Hjelstuen, L. Beneteau, B. Froelich\",\"doi\":\"10.1109/ESSCIR.2005.1541616\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A mixed signal ASIC that implements an ultrasound front end receiver in a 0.6/spl mu/m BiCMOS HotASIC/spl reg/ technology is described. The ASIC includes a low noise amplifier (LNA), a programmable gain amplifier (PGA), an output differential amplifier (ODA), a second order sigma delta modulator (SDM) and is the most compact system for high temperature ultrasound applications reported in literature. The circuit has a programmable gain and is designed for measuring the signal response (200kHz to 700kHz) from an ultrasound transducer. At 48MHz clock frequency and 200/spl deg/C the power consumption is 85mW from a single 5V supply. The die area of the chip is 5.52 mm/sup 2/.\",\"PeriodicalId\":239980,\"journal\":{\"name\":\"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2005.1541616\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2005.1541616","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
介绍了一种以0.6/spl μ m BiCMOS HotASIC/spl reg/技术实现超声前端接收器的混合信号ASIC。ASIC包括一个低噪声放大器(LNA),一个可编程增益放大器(PGA),一个输出差分放大器(ODA),一个二阶σ δ调制器(SDM),是文献报道的高温超声应用中最紧凑的系统。该电路具有可编程增益,设计用于测量来自超声波换能器的信号响应(200kHz至700kHz)。在48MHz时钟频率和200/spl度/C下,单个5V电源的功耗为85mW。芯片的模面积为5.52 mm/sup 2/。
A BiCMOS ultrasound front end signal processor for high temperature applications
A mixed signal ASIC that implements an ultrasound front end receiver in a 0.6/spl mu/m BiCMOS HotASIC/spl reg/ technology is described. The ASIC includes a low noise amplifier (LNA), a programmable gain amplifier (PGA), an output differential amplifier (ODA), a second order sigma delta modulator (SDM) and is the most compact system for high temperature ultrasound applications reported in literature. The circuit has a programmable gain and is designed for measuring the signal response (200kHz to 700kHz) from an ultrasound transducer. At 48MHz clock frequency and 200/spl deg/C the power consumption is 85mW from a single 5V supply. The die area of the chip is 5.52 mm/sup 2/.