Electrical measurement of alignment for 3D stacked chips

Abstract

This paper presents an electronic system based on integrated CMOS capacitive sensors that enables to determine the alignment between two chips assembled in a three-dimensional (3D) stacking configuration. Two different interface circuits are described for the on-chip measurement of alignment along vertical Z-axis and lateral X/Y-axis. A test chip has been fabricated in 0.13/spl mu/m, 6 metal standard CMOS process to test the multi-axis alignment system based on 3D sensors. A capacitive charge variation of 1 fF over 15fF corresponding to a resolution accuracy of 0.5/spl mu/m over a range of 50/spl mu/m has been measured. Sensors are 120/spl mu/m /spl times/ 30/spl mu/m and power consumption is 200/spl mu/W.