18ghz, 10.9 dbm全集成功率放大器，在130纳米CMOS中具有23.5%的PAE

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541578

C. Cao, H. Xu, Yu Su, K. O

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引用次数: 27

摘要

采用UMC 130纳米数字CMOS工艺，制备了饱和输出功率为10.9 dbm、最大PAE为23.5 %的18 ghz全集成e类功率放大器。在饱和输出时，所需输入功率电平为-5dBm, PA从V/sub DD/=1.5V消耗35mA。该放大器是单端放大器，包括一个2级前置放大器和一个驱动级。利用驱动放大器的不稳定性，采用锁模技术来提高输出级栅极的驱动性能。模式锁定将PAE提高了/spl sim/3%，并将所需的输入功率降低了/spl sim/6dB，以获得相同的输出电平。

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An 18-GHz, 10.9-dBm fully-integrated power amplifier with 23.5% PAE in 130-nm CMOS

An 18-GHz fully integrated class-E power amplifier with 10.9-dBm saturated output power, and 23.5-% maximum PAE is fabricated in the UMC 130-nm digital CMOS process. At the saturated output, the required input power level is -5dBm and PA consumes 35mA from V/sub DD/=1.5V. The amplifier is single-ended and includes a 2-stage pre-amplifier and a driver stage. A mode-locking technique exploiting the instability of driver amplifier is used to improve the drive for the gate of output stage. The mode-locking improves PAE by /spl sim/3% and reduces the required input power level by /spl sim/6dB to get same output level.

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来源期刊

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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