3.33Gb/s(1200,720)低密度奇偶校验码解码器

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541597

Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee

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引用次数: 39

摘要

本文提出了一种基于不规则奇偶校验矩阵的(1200,720)LDPC解码器。为了实现更高的芯片密度和更少的关键路径延迟，所提出的体系结构的特点是数据重排序，这样在消息存储器和计算单元之间只有一个特定的数据总线存在。此外，LDPC解码器还可以同时处理两个不同的码字，以提高吞吐量和数据路径效率。芯片实现后，在21.23mm/sup / 0.18/spl mu/m硅片面积下，经过8次解码迭代，数据速率达到3.33Gb/s。另一款0.13/spl mu/m的芯片采用10.24mm/sup 2/ core，在1.02V电源下可以进一步达到5.92Gb/s的数据速率。

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A 3.33Gb/s (1200,720) low-density parity check code decoder

In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm/sup 2/ 0.18/spl mu/m silicon area. The other 0.13/spl mu/m chip with the 10.24mm/sup 2/ core can further reach a 5.92Gb/s data rate under 1.02V supply.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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