A 220mW 14b 40MSPS gain calibrated pipelined ADC

Abstract

In this paper, a pipelined ADC based on digital calibration of gain errors is presented. The ADC achieves 85dBFS SNDR and 84dBFS SFDR with a 50dB DC gain OTA in the first stage. The calibration algorithm is based on test signal injection. At 40MSPS the power dissipation is 220mW from a 2.5V supply. The ADC is designed in a 0.25/spl mu/m CMOS process and occupies an area of 6.5mm/sup 2/.