一个220mW 14b 40MSPS增益校准的流水线ADC

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541585

J. Bjørnsen, Øystein Moldsvor, Trond Sæther, T. Ytterdal

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引用次数: 5

摘要

本文提出了一种基于增益误差数字校准的流水线ADC。ADC在第一级实现85dBFS SNDR和84dBFS SFDR, DC增益OTA为50dB。该标定算法基于测试信号注入。在40MSPS时，2.5V电源的功耗为220mW。ADC采用0.25/spl mu/m CMOS工艺设计，占地面积为6.5mm/sup / 2/。

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A 220mW 14b 40MSPS gain calibrated pipelined ADC

In this paper, a pipelined ADC based on digital calibration of gain errors is presented. The ADC achieves 85dBFS SNDR and 84dBFS SFDR with a 50dB DC gain OTA in the first stage. The calibration algorithm is based on test signal injection. At 40MSPS the power dissipation is 220mW from a 2.5V supply. The ADC is designed in a 0.25/spl mu/m CMOS process and occupies an area of 6.5mm/sup 2/.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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