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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.最新文献

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A 5.5 V SOPA line driver in a standard 1.2 V 0.13 /spl mu/m CMOS technology 5.5 V SOPA线路驱动器采用标准的1.2 V 0.13 /spl mu/m CMOS技术
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541620
B. Serneels, M. Steyaert, W. Dehaene
{"title":"A 5.5 V SOPA line driver in a standard 1.2 V 0.13 /spl mu/m CMOS technology","authors":"B. Serneels, M. Steyaert, W. Dehaene","doi":"10.1109/ESSCIR.2005.1541620","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541620","url":null,"abstract":"In this work a high voltage line driver, using a self-oscillating power amplifier (SOPA) in a digital 1.2 V 0.13 /spl mu/m CMOS technology is presented. A self biasing cascode topology allows the line driver to operate at 4.5 times the nominal supply voltage. Oxide breakdown and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The realized prototype delivers a 35 MHz PWM square wave with a 4.6 V swing in a 7.1 /spl Omega/ load with an efficiency of 62%. The chip achieves a spurious free dynamic range (SFDR) of 52 dB while driving a 1 MHz sine wave. A missing tone power ratio (MTPR) of 50 dB has been measured for a DMT signal up to 1.1 MHz with a crest factor of 14 dB.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"C-27 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132531109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A novel current-mode very low power analog CMOS four quadrant multiplier 一种新型电流模式极低功耗模拟CMOS四象限乘法器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541668
M. Gravati, M. Valle, G. Ferri, N. Guerrini, L. Reyes
{"title":"A novel current-mode very low power analog CMOS four quadrant multiplier","authors":"M. Gravati, M. Valle, G. Ferri, N. Guerrini, L. Reyes","doi":"10.1109/ESSCIR.2005.1541668","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541668","url":null,"abstract":"In this paper, a novel current mode CMOS four-quadrant analog multiplier circuit is presented. The multiplication is implemented by four translinear loops with MOS transistors operating in weak inversion. Information carrying signals are differential balanced currents. The multiplier circuit has been implemented in a test chip in a standard 0.35 /spl mu/m CMOS technology. The experimental measurements (dc bias current of 250 nA and a power supply of 2.0 V) show a bandwidth of 200 kHz and a THD figure value lower than 0.9 %. The multiplier features a wide signal dynamic range and linearity, low power consumption (the maximum power consumption is of 5.5/spl middot/10/sup -6/ W) and very low area (18.7 /spl middot/10/sup -3/ mm/sup 2/). The multiplier is suitable for a wide range of analog signal processing applications. Due to the low power and silicon area consumption, scalability and modularity can be also easily integrated in massive parallel systems.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132663056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 88
A PMOS-switch based charge pump, allowing lost cost implementation on a CMOS standard process 基于pmos开关的电荷泵，允许在CMOS标准工艺上实现成本损失
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541562
E. Racape, J. Daga
{"title":"A PMOS-switch based charge pump, allowing lost cost implementation on a CMOS standard process","authors":"E. Racape, J. Daga","doi":"10.1109/ESSCIR.2005.1541562","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541562","url":null,"abstract":"A 4-phase charge pump based on the low-voltage PMOS switching circuitry has been implemented in a 0.18/spl mu/m CMOS standard process, without any additional masking and process steps. The use of low-voltage PMOS switches overcomes the intrinsic limitations of high voltage NMOS devices such as: poor drive, large parasitic capacitance, threshold voltage sensitivity to body bias and temperature. Using the proposed circuitry, up to 14v output voltage has been measured on a 11-stage implementation powered at 1.2v, resulting in 97% of Vdd average gain per stage with capacitive loading only. In addition, nearly temperature independent efficiency of 53% has been measured on an extended Vdd range, for different current loads.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115409756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS 65nm CMOS亚阈值SRAM静态噪声裕度分析
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541635
B. Calhoun, A. Chandrakasan
{"title":"Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS","authors":"B. Calhoun, A. Chandrakasan","doi":"10.1109/ESSCIR.2005.1541635","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541635","url":null,"abstract":"This paper evaluates the static noise margin (SNM) of 6T SRAM bitcells operating in sub-threshold. We analyze the dependence of SNM during both hold and read modes on supply voltage, temperature, transistor sizes, local transistor mismatch due to random doping variation, and global process variation in a commercial 65nm technology. We analyze the statistical distribution of SNM with process variation and provide a model for the tail of the PDF that dominates SNM failures.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122352396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 120
A CMOS-based sensor array system for chemical and biochemical applications 基于cmos的传感器阵列系统，用于化学和生化应用
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541630
M. Zimmermann, T. Volden, Kai-Uwe Kirstein, S. Hafizovic, J. Lichtenberg, A. Hierlemann
{"title":"A CMOS-based sensor array system for chemical and biochemical applications","authors":"M. Zimmermann, T. Volden, Kai-Uwe Kirstein, S. Hafizovic, J. Lichtenberg, A. Hierlemann","doi":"10.1109/ESSCIR.2005.1541630","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541630","url":null,"abstract":"A monolithic, integrated sensor system is presented that features microcantilevers as transducer elements for simultaneous detection of multiple (bio)chemical compounds. The cantilevers can be coated with receptors specific to certain analytes (e.g., antibodies for antigens) or with less specific polymer layers to detect a broad range of analytes (such as volatile organic compounds). The analyte absorption or binding changes the surface stress of the cantilevers, which is detected by an integrated Wheatstone bridge. The integrated readout circuitry includes a chopper-stabilized amplifier, which performs a low-noise, low-offset amplification of the /spl mu/V-range sensor signal. Additional low-pass filtering and a programmable offset-compensation stage allow for a high signal-to-noise ratio. A sigma-delta analog-digital converter (/spl Sigma//spl Delta/-ADC) delivers the measured data to the outside world via a digital serial interface. The monolithic integration reduces the sensitivity to external interference and enables autonomous device operation. The integrated sensor array can easily be scaled to higher number of cantilevers.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121087544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Optimally-placed twists in global on-chip differential interconnects 全球片上差分互连的最佳位置扭转
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541663
E. Mensink, D. Schinkel, E. Klumperink, E. V. Tuijl, B. Nauta
{"title":"Optimally-placed twists in global on-chip differential interconnects","authors":"E. Mensink, D. Schinkel, E. Klumperink, E. V. Tuijl, B. Nauta","doi":"10.1109/ESSCIR.2005.1541663","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541663","url":null,"abstract":"A bus-transceiver test chip in 0.13 /spl mu/m CMOS achieves 3 Gb/s/ch over 10 mm long uninterrupted differential interconnect of only 0.8 /spl mu/m pitch. As crosstalk would impede this high data rate, twists are used. Analysis shows that the optimal positions of the twists depend on the termination of the interconnect. Theory and measurements show that only one twist at 50% of the even interconnects, two twists at 30% and 70% of the odd interconnects and equal source and load impedances are very effective in mitigating the crosstalk.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122766406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 1 watt audio amplifier in a standard digital 90-nm CMOS technology 一个标准数字90纳米CMOS技术的1瓦音频放大器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541608
R. Becker, W. Groeneweg
{"title":"A 1 watt audio amplifier in a standard digital 90-nm CMOS technology","authors":"R. Becker, W. Groeneweg","doi":"10.1109/ESSCIR.2005.1541608","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541608","url":null,"abstract":"An audio amplifier in a standard 90-nm CMOS technology is designed for direct battery hook-up in a mobile phone. Special techniques have been applied to run it from a supply voltage of up to 5.5 V. The circuit does not require a dedicated supply voltage generator, it can be integrated on the same chip with the digital signal processor, provides high output power, good power supply rejection and good efficiency.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125113370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 10Gb/s, 3.3V, laser/modulator driver with high power efficiency 10Gb/s, 3.3V，高功率效率的激光/调制器驱动器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541651
M. Sanduleanu, E. Stikvoort
{"title":"A 10Gb/s, 3.3V, laser/modulator driver with high power efficiency","authors":"M. Sanduleanu, E. Stikvoort","doi":"10.1109/ESSCIR.2005.1541651","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541651","url":null,"abstract":"The presented laser/modulator driver for optical communication aims at low power dissipation. The single-ended output with a push-pull driver allows a 3.3 V supply while leaving 1.8 V for the laser. The laser is DC coupled to the open collector output stage so that the DC bias current of the driver is used for biasing of the laser. The minimum supply voltage of the IC is 2.7 V. The circuit was realised in the Philips QUBiC4 BiCMOS IC process with a cut off frequency f/sub T/ of 37GHz. The chip was mounted as a die on board and the electrical output signal was measured. The signal-to-noise ratio is 7.44dB, the measured bit error rate is <10/sup -12/. The minimal rise/fall time is about 42 ps and the measured rms jitter is 5.3 ps. The active area of the IC is 800/spl times/700 /spl mu/m/sup 2/. The dissipation is 240 mW for a supply voltage of 3.3 V and room temperature.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125962643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A programmable OEIC for laser applications in the range from 405nm to 780nm 用于405nm至780nm激光应用的可编程OEIC
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541654
C. Seidl, Harald Schatzmayr, J. Sturm, S. Groiss, M. Leifhelm, D. Spitzer, H. Schaunig, H. Zimmermann
{"title":"A programmable OEIC for laser applications in the range from 405nm to 780nm","authors":"C. Seidl, Harald Schatzmayr, J. Sturm, S. Groiss, M. Leifhelm, D. Spitzer, H. Schaunig, H. Zimmermann","doi":"10.1109/ESSCIR.2005.1541654","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541654","url":null,"abstract":"An OEIC with integrated PIN photodiodes for optical receiver applications like CD, DVD, HDDVD or Blu-ray, is presented. For the fast channels a maximum transimpedance of 465k/spl Omega/ or a sensitivity of 116mV//spl mu/W for 405nm with a bandwidth of 145MHz was achieved. The power consumption of 162.5mW at 5V is low enough for implementation in optical pickup units.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130655060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Scalable circuits for supply noise measurement 用于电源噪声测量的可扩展电路
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541660
V. Abramzon, E. Alon, B. Nezamfar, M. Horowitz
{"title":"Scalable circuits for supply noise measurement","authors":"V. Abramzon, E. Alon, B. Nezamfar, M. Horowitz","doi":"10.1109/ESSCIR.2005.1541660","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541660","url":null,"abstract":"This paper discusses techniques to allow high-resolution supply noise measurements in advanced CMOS technologies without the overhead of voltage references or separate power supplies. In addition to improving the existing sample and hold-based system, we propose a new technique that uses a very short integration time in the voltage-controlled oscillator (VCO)-based A/D converter and hence removes the difficult-to-scale sample and hold circuit. Each conversion results in a low-resolution measurement; however the measurements are intrinsically dithered so that resolution can be increased by averaging multiple conversions. Both sample and hold-based and averaging-based systems are implemented in a 90nm SOI process as part of a characterization test chip for the parallel interface described in (Chang et al., 2005). Measurement results show both systems are capable of measuring supply noise down to 5mV with bandwidths well in the GHz range.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122129234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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