5.5 V SOPA线路驱动器采用标准的1.2 V 0.13 /spl mu/m CMOS技术

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541620

B. Serneels, M. Steyaert, W. Dehaene

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引用次数: 22

摘要

本文介绍了一种采用自振荡功率放大器(SOPA)的1.2 V 0.13 /spl mu/m数字CMOS技术的高压线路驱动器。自偏置级联码拓扑允许线路驱动器在4.5倍标称电源电压下工作。由于驱动器在主流CMOS技术设计规则规定的电压范围内工作，因此氧化物击穿和热载流子降解被最小化。实现的原型在7.1 /spl ω /负载下提供35 MHz PWM方波，摆幅为4.6 V，效率为62%。该芯片在驱动1 MHz正弦波时实现52 dB的无杂散动态范围(SFDR)。在峰值系数为14 dB的1.1 MHz DMT信号中，缺失音功率比(MTPR)为50 dB。

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A 5.5 V SOPA line driver in a standard 1.2 V 0.13 /spl mu/m CMOS technology

In this work a high voltage line driver, using a self-oscillating power amplifier (SOPA) in a digital 1.2 V 0.13 /spl mu/m CMOS technology is presented. A self biasing cascode topology allows the line driver to operate at 4.5 times the nominal supply voltage. Oxide breakdown and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The realized prototype delivers a 35 MHz PWM square wave with a 4.6 V swing in a 7.1 /spl Omega/ load with an efficiency of 62%. The chip achieves a spurious free dynamic range (SFDR) of 52 dB while driving a 1 MHz sine wave. A missing tone power ratio (MTPR) of 50 dB has been measured for a DMT signal up to 1.1 MHz with a crest factor of 14 dB.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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