65nm CMOS亚阈值SRAM静态噪声裕度分析

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541635

B. Calhoun, A. Chandrakasan

{"title":"65nm CMOS亚阈值SRAM静态噪声裕度分析","authors":"B. Calhoun, A. Chandrakasan","doi":"10.1109/ESSCIR.2005.1541635","DOIUrl":null,"url":null,"abstract":"This paper evaluates the static noise margin (SNM) of 6T SRAM bitcells operating in sub-threshold. We analyze the dependence of SNM during both hold and read modes on supply voltage, temperature, transistor sizes, local transistor mismatch due to random doping variation, and global process variation in a commercial 65nm technology. We analyze the statistical distribution of SNM with process variation and provide a model for the tail of the PDF that dominates SNM failures.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"120","resultStr":"{\"title\":\"Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS\",\"authors\":\"B. Calhoun, A. Chandrakasan\",\"doi\":\"10.1109/ESSCIR.2005.1541635\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper evaluates the static noise margin (SNM) of 6T SRAM bitcells operating in sub-threshold. We analyze the dependence of SNM during both hold and read modes on supply voltage, temperature, transistor sizes, local transistor mismatch due to random doping variation, and global process variation in a commercial 65nm technology. We analyze the statistical distribution of SNM with process variation and provide a model for the tail of the PDF that dominates SNM failures.\",\"PeriodicalId\":239980,\"journal\":{\"name\":\"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"120\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2005.1541635\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2005.1541635","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 120

摘要

本文评估了在亚阈值下工作的6T SRAM位元的静态噪声裕度(SNM)。我们分析了在保持和读取模式下SNM对电源电压、温度、晶体管尺寸、随机掺杂变化导致的局部晶体管失配以及商用65nm技术的全局工艺变化的依赖性。我们分析了SNM随工艺变化的统计分布，并为主导SNM失效的PDF尾部提供了一个模型。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS

This paper evaluates the static noise margin (SNM) of 6T SRAM bitcells operating in sub-threshold. We analyze the dependence of SNM during both hold and read modes on supply voltage, temperature, transistor sizes, local transistor mismatch due to random doping variation, and global process variation in a commercial 65nm technology. We analyze the statistical distribution of SNM with process variation and provide a model for the tail of the PDF that dominates SNM failures.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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