A 5.5 V SOPA line driver in a standard 1.2 V 0.13 /spl mu/m CMOS technology

Abstract

In this work a high voltage line driver, using a self-oscillating power amplifier (SOPA) in a digital 1.2 V 0.13 /spl mu/m CMOS technology is presented. A self biasing cascode topology allows the line driver to operate at 4.5 times the nominal supply voltage. Oxide breakdown and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The realized prototype delivers a 35 MHz PWM square wave with a 4.6 V swing in a 7.1 /spl Omega/ load with an efficiency of 62%. The chip achieves a spurious free dynamic range (SFDR) of 52 dB while driving a 1 MHz sine wave. A missing tone power ratio (MTPR) of 50 dB has been measured for a DMT signal up to 1.1 MHz with a crest factor of 14 dB.