Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.最新文献_第7页

A 5-GHz BiCMOS variable-gain low noise amplifier with inductorless low-gain branch 具有无电感低增益支路的5 ghz BiCMOS变增益低噪声放大器

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541600

Mingxu Liu, J. Craninckx

引用次数: 4

IP2 calibrator using common mode feedback circuitry IP2校准器使用共模反馈电路

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541602

Woonyun Kim, Sung-Gi Yang, Yeon-kug Moon, J. Yu, Heeseon Shin, Wooseung Choo, Byeong-ha Park

引用次数: 5

A low-power 2-GSample/s comparator in 120 nm CMOS technology 采用120nm CMOS技术的低功耗2-GSample/s比较器

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541671

Bernard Goll, H. Zimmermann

引用次数: 7

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18/spl mu/m digital CMOS technology 基于CDR的多通道3.5mW/Gbps/通道门控振荡器，采用0.18/spl mu/m数字CMOS技术

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541592

A. Tajalli, P. Muller, S. M. Atarodi, Y. Leblebici

引用次数: 9

A built-in I/sub DDQ/ testing circuit 内置I/sub DDQ/测试电路

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541662

S. Matakias, Y. Tsiatouhas, A. Arapoyanni, T. Haniotakis, G. Prenat, S. Mir

引用次数: 1

A 0.18/spl mu/m CMOS switched capacitor voltage modulator 一个0.18/spl mu/m CMOS开关电容电压调制器

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541638

Koen Cornelissens, P. Reynaert, M. Steyaert

引用次数: 1

Differential image sensor with high common mode rejection 具有高共模抑制的差分图像传感器

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541665

M. Innocent, G. Meynants

引用次数: 4

120nm CMOS OPAMP with 690 MHz f/sub T/ and 128 dB DC gain 120nm CMOS OPAMP, 690 MHz f/sub /和128 dB DC增益

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541607

Franz Schlögl, H. Zimmermann

引用次数: 7

A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs 具有宽范围操作和多相输出的快速锁定混合模式DLL

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541591

Kuo-Hsing Cheng, Y. Lo

{"title":"A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs","authors":"Kuo-Hsing Cheng, Y. Lo","doi":"10.1109/ESSCIR.2005.1541591","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541591","url":null,"abstract":"This paper describes a fast-lock mixed-mode delay-locked loop (MMDLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for frequency range selector, a start-up circuit and coarse tune circuit to offer the faster lock time. And the multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide the wide locked range and low-jitter performance. The charge pump circuit is implemented by digital controlled scheme to reach bandwidth tracking. The chip has been fabricated using the TSMC 0.25-/spl mu/m single-poly five-metal CMOS process with a 2.5 V power supply voltage. From the measurement results, this DLL can operate correctly when the input clock frequency is changed from 32 to 320 MHz and generate ten-phase clocks within just one clock cycle. Moreover, the proposed DLL can solve the problem of the false locking associated with conventional DLLs and wide-range operation. At 320 MHz, the measured peak-to-peak jitter and root-mean-squared jitter are 37.2 ps and 2.492 ps, respectively. Furthermore, the locking time is less than 22 clock cycles based on the HSPICE simulation results. The DLL occupies smaller area (0.32 /spl times/ 0.22 mm/sup 2/) and dissipates less power (15 mW) than other wide-range DLLs presented in Y. J. Jung et al. (2001), D. J. Foley et al. (2001), Y. Moon et al. (2000), B. W. Garlepp et al. (1999), H. H. Chang et al. (2002), S. Sidiropoulos et al. (1997) and S. J. Kim et al. (2002).","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131251419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Design for manufacturing in the nanoscale era 纳米时代的制造设计

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541593

C. Bittlestone

引用次数: 0