基于CDR的多通道3.5mW/Gbps/通道门控振荡器，采用0.18/spl mu/m数字CMOS技术

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI:10.1109/ESSCIR.2005.1541592

A. Tajalli, P. Muller, S. M. Atarodi, Y. Leblebici

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引用次数: 9

摘要

本文提出了一种具有8个并行通道的极低功耗时钟和数据恢复(CDR)电路，实现了20 Gbps的总数据速率。采用结构自顶向下的设计方法，在满足短距离接收机所需规格的同时，最大限度地降低了功耗。采用0.18/spl mu/m的数字CMOS技术实现，总功耗为70.2mW或3.51mW/Gbps/ch，每个通道占用0.045/spl mu/m/sup 2/硅面积。

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A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18/spl mu/m digital CMOS technology

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18/spl mu/m digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/ch and each channel occupies 0.045/spl mu/m/sup 2/ silicon area.

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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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