A low-power 2-GSample/s comparator in 120 nm CMOS technology

Abstract

This paper presents a comparator in 120nm digital CMOS technology with a supply voltage of 1.5V. In contrast to common comparator structures a delayed reset signal is used to enhance the output voltage difference with the help of charge injection. Furthermore the body effect of p-MOS transistors with their separated n-wells are used to lower their threshold voltage to have an increase in resolution. For characterization several BER (bit-error-rate) measurements on the comparator have been made. For a BER of 109 the comparator is able to detect an input voltage difference of 9.5mV at a clock frequency of 1.5GHz and 16mV at 2.0GHz. The maximum power consumption of the comparator with two following additional transfer stages is 360/spl mu/W at 2.0GHz.