A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs

Abstract

This paper describes a fast-lock mixed-mode delay-locked loop (MMDLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for frequency range selector, a start-up circuit and coarse tune circuit to offer the faster lock time. And the multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide the wide locked range and low-jitter performance. The charge pump circuit is implemented by digital controlled scheme to reach bandwidth tracking. The chip has been fabricated using the TSMC 0.25-/spl mu/m single-poly five-metal CMOS process with a 2.5 V power supply voltage. From the measurement results, this DLL can operate correctly when the input clock frequency is changed from 32 to 320 MHz and generate ten-phase clocks within just one clock cycle. Moreover, the proposed DLL can solve the problem of the false locking associated with conventional DLLs and wide-range operation. At 320 MHz, the measured peak-to-peak jitter and root-mean-squared jitter are 37.2 ps and 2.492 ps, respectively. Furthermore, the locking time is less than 22 clock cycles based on the HSPICE simulation results. The DLL occupies smaller area (0.32 /spl times/ 0.22 mm/sup 2/) and dissipates less power (15 mW) than other wide-range DLLs presented in Y. J. Jung et al. (2001), D. J. Foley et al. (2001), Y. Moon et al. (2000), B. W. Garlepp et al. (1999), H. H. Chang et al. (2002), S. Sidiropoulos et al. (1997) and S. J. Kim et al. (2002).