{"title":"纳米时代的制造设计","authors":"C. Bittlestone","doi":"10.1109/ESSCIR.2005.1541593","DOIUrl":null,"url":null,"abstract":"Design for manufacturing, DFM, has been an increasingly important area for several years. Lithography at 90nm, 65nm, and below takes DFM into the critical zone for designers. Designers must now use extreme measures to achieve full technology entitlement of performance, power, area, reliability and yield. This presentations focus on major physical DFM effects and their impact on designers. It uses real life examples from 90 and 65nm to illustrate problems and trends. Several focus issues are linked to design impact and onto rules, modeling and other mitigation techniques. This talks touch on several critical areas such as RET/OPC/litho/etch, simulation, layout rules, and extraction. Both systematic and random effects are mentioned. Also covered are examples of some methods that are used to model or design around these issues to enable designers to meet technology entitlement goals.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design for manufacturing in the nanoscale era\",\"authors\":\"C. Bittlestone\",\"doi\":\"10.1109/ESSCIR.2005.1541593\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design for manufacturing, DFM, has been an increasingly important area for several years. Lithography at 90nm, 65nm, and below takes DFM into the critical zone for designers. Designers must now use extreme measures to achieve full technology entitlement of performance, power, area, reliability and yield. This presentations focus on major physical DFM effects and their impact on designers. It uses real life examples from 90 and 65nm to illustrate problems and trends. Several focus issues are linked to design impact and onto rules, modeling and other mitigation techniques. This talks touch on several critical areas such as RET/OPC/litho/etch, simulation, layout rules, and extraction. Both systematic and random effects are mentioned. Also covered are examples of some methods that are used to model or design around these issues to enable designers to meet technology entitlement goals.\",\"PeriodicalId\":239980,\"journal\":{\"name\":\"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2005.1541593\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2005.1541593","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design for manufacturing, DFM, has been an increasingly important area for several years. Lithography at 90nm, 65nm, and below takes DFM into the critical zone for designers. Designers must now use extreme measures to achieve full technology entitlement of performance, power, area, reliability and yield. This presentations focus on major physical DFM effects and their impact on designers. It uses real life examples from 90 and 65nm to illustrate problems and trends. Several focus issues are linked to design impact and onto rules, modeling and other mitigation techniques. This talks touch on several critical areas such as RET/OPC/litho/etch, simulation, layout rules, and extraction. Both systematic and random effects are mentioned. Also covered are examples of some methods that are used to model or design around these issues to enable designers to meet technology entitlement goals.