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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.最新文献

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A 3.5Gbit/s post-amplifier in 0.18/spl mu/m CMOS 3.5Gbit/s后置放大器，0.18/spl mu/m CMOS
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541652
C. Hermans, M. Steyaert
{"title":"A 3.5Gbit/s post-amplifier in 0.18/spl mu/m CMOS","authors":"C. Hermans, M. Steyaert","doi":"10.1109/ESSCIR.2005.1541652","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541652","url":null,"abstract":"A postamplifier with output buffer implemented in a standard 0.18/spl mu/m 1.8V CMOS technology is proposed. Using broadband techniques for both postamplifier and output buffer, highspeed operation has been achieved. For a differential 10mV/sub pp/ 2/sup 31/-1 pseudo random bit sequence, a bit error rate of 5/spl middot/10/sup -12/ at 3.5Gbit/s has been measured. At lower bitrates the bit error rate is even lower: a 1 Gbit/s 10mV/sub pp/, input signal results in a bit error rate of 7/spl middot/10/sup -14/. The rms jitter is 12ps. The postamplifier circuit consumes only 19mA from a 1.8V power supply.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134316442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Notice of Violation of IEEE Publication PrinciplesA 12.5GHz SiGe BICMOS limiting amplifier using a dual offset cancellation loop 一种采用双偏置抵消回路的12.5GHz SiGe BICMOS限幅放大器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541567
A. Maxim, D. Antrik
{"title":"Notice of Violation of IEEE Publication PrinciplesA 12.5GHz SiGe BICMOS limiting amplifier using a dual offset cancellation loop","authors":"A. Maxim, D. Antrik","doi":"10.1109/ESSCIR.2005.1541567","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541567","url":null,"abstract":"A 12.5GHz limiting amplifier was realized in a 0.2μm 90GHz f/sub T/ SiGe BICMOS process. The signal path was implemented as a cascade of emitter followers and differential stages using multiple capacitive peaking networks. The output offset voltage was reduced to fractions of mV by using a dual active offset cancellation loop having the compensation capacitance integrated on-chip due to a Miller multiplication architecture. ICs specifications include: >60dB signal path gain, <0.2mV output offset voltage, >12.5GHz signal path bandwidth, 1mV input sensitivity, <25ps rise/ fall time, <15ps deterministic jitter, 1.5×1.5mm/sup 2/ die area and 25mA current from a 3.3V 7±10% supply voltage.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132226305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
GMSK modulation of subharmonic injection locked oscillators 次谐波注入锁定振荡器的GMSK调制
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541568
T. Finateu, J. Bégueret, Y. Deval, F. Badets
{"title":"GMSK modulation of subharmonic injection locked oscillators","authors":"T. Finateu, J. Bégueret, Y. Deval, F. Badets","doi":"10.1109/ESSCIR.2005.1541568","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541568","url":null,"abstract":"This paper presents theoretical results on phase modulation of injection locked oscillators. Experimental results on a 2-GHz fifth subharmonic injection locked oscillator (SBILO) integrated in a 0.35-/spl mu/m BiCMOS STMicroelectronics technology are presented. Measured phase error added by the SBILO once locked by a GMSK modulated signal is negligible.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132131760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
ESD-protected CMOS 3-5 GHz wideband LNA+PGA design for UWB 超宽带防静电CMOS 3-5 GHz宽带LNA+PGA设计
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541599
R. Salerno, M. Tiebout, Herrmann Paule, M. Streibl, C. Sandner, K. Kropf
{"title":"ESD-protected CMOS 3-5 GHz wideband LNA+PGA design for UWB","authors":"R. Salerno, M. Tiebout, Herrmann Paule, M. Streibl, C. Sandner, K. Kropf","doi":"10.1109/ESSCIR.2005.1541599","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541599","url":null,"abstract":"This work presents the design of a low noise amplifier (LNA) and programmable gain amplifier (PGA) set targeted for a fully integrated 3-5 GHz UWB transceiver in standard 0.13 /spl mu/m CMOS. The circuit designs were optimized for best performance in terms of noise figure, linearity, gain, gain flatness, power consumption and ESD-hardness. For minimal crosstalk risk, differential designs with small areas were preferred. Measured LNA+PGA testchip shows a gain of 25.8 dB, with a gain flatness of 1 dB from 3-5 GHz, a NF of 3.6 dB at 3 GHz, an input compression point of -22.7dBm and an HBM ESD hardness of 1.5 kV at a total power consumption of 45 mW.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128521824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Phase noise degradation of LC-tank VCOs due to substrate noise and package coupling 衬底噪声和封装耦合对LC-tank vco相位噪声的影响
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541569
M. Méndez, D. Mateo, X. Aragonès, J. González
{"title":"Phase noise degradation of LC-tank VCOs due to substrate noise and package coupling","authors":"M. Méndez, D. Mateo, X. Aragonès, J. González","doi":"10.1109/ESSCIR.2005.1541569","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541569","url":null,"abstract":"The present work addresses the investigation of phase noise degradation of LC-tank VCOs due to realistic digitally originated substrate noise. The dominant mechanisms by which this noise is coupled to the output of the oscillator due to the substrate and the package are analyzed, indicating that both noise at low frequencies and at high frequencies around the oscillation fundamental significantly degrade phase noise.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128084781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Low leakage design of LUT-based FPGAs 基于lut的fpga低泄漏设计
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541582
Andrea Lodi, L. Ciccarelli, D. Loparco, R. Canegallo, R. Guerrieri
{"title":"Low leakage design of LUT-based FPGAs","authors":"Andrea Lodi, L. Ciccarelli, D. Loparco, R. Canegallo, R. Guerrieri","doi":"10.1109/ESSCIR.2005.1541582","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541582","url":null,"abstract":"Moving to the 90nm node and below, in FPGA architectures, where there's a large number of inactive transistors, power consumption due to subthreshold current becomes more and more relevant compared with the switching one. In this paper we analyze the leakage current associated to look up tables, the basic elaboration units of LUT-based FPGAs, giving a characterization in terms of timing performance, inactive and active leakage power consumption. We propose a circuit implementation to reduce leakage, avoiding delay and silicon area increase. The adopted solutions are based on multi-threshold and self reverse biasing techniques. As results we reduce the inactive leakage power by 88%, the active one by 64%, having 5% delay degradation and a negligible silicon area increase.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121912804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 1 V, 26 /spl mu/W extended temperature range band-gap reference in 130-nm CMOS technology 一个1 V, 26 /spl mu/W的扩展温度范围的带隙参考在130纳米CMOS技术
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541670
A. Cabrini, G. Sandre, L. Gobbi, P. Malcovati, M. Pasotti, M. Poles, F. Rigoni, G. Torelli
{"title":"A 1 V, 26 /spl mu/W extended temperature range band-gap reference in 130-nm CMOS technology","authors":"A. Cabrini, G. Sandre, L. Gobbi, P. Malcovati, M. Pasotti, M. Poles, F. Rigoni, G. Torelli","doi":"10.1109/ESSCIR.2005.1541670","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541670","url":null,"abstract":"This paper presents a fully CMOS band-gap reference for extended temperature range (from -50 /spl deg/C to 160 /spl deg/C) applications. The proposed solution provides an output voltage of 798 mV with a power supply as low as 1 V. The measured output voltage variations as a function of temperature (-50 /spl deg/C to 160 /spl deg/C) and power supply (1 V to 2 V) are 6.64 ppm//spl deg/C and 248 ppm/V, respectively. High accuracy is achieved by minimizing the operational amplifier offset. Power consumption is approximately equal to 26 /spl mu/W (supply voltage = 1 V). Silicon area is 0.02 mm/sup 2/.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122295377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Realization of a simple high-value grounded linear resistance in CMOS technology
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541640
P. Langlois, John T. Taylor, A. Demosthenous
{"title":"Realization of a simple high-value grounded linear resistance in CMOS technology","authors":"P. Langlois, John T. Taylor, A. Demosthenous","doi":"10.1109/ESSCIR.2005.1541640","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541640","url":null,"abstract":"A resistor circuit suitable for realizing high-values of resistance (>10M/spl Omega/), linear over signal amplitudes of /spl plusmn/100mV is demonstrated. The resistor is variable over a range of /spl plusmn/10%. The design is relatively simple and can be used to AC couple low-frequency analogue signal processing blocks, for example in biomedical engineering applications.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126148362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs 用于192mbps无线局域网的MIMO-OFDM收发器的ASIC实现
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541598
D. Perels, S. Haene, P. Luethi, A. Burg, N. Felber, W. Fichtner, H. Bölcskei
{"title":"ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs","authors":"D. Perels, S. Haene, P. Luethi, A. Burg, N. Felber, W. Fichtner, H. Bölcskei","doi":"10.1109/ESSCIR.2005.1541598","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541598","url":null,"abstract":"Next generation wireless local area networks (WLANs) such as the IEEE 802.11a standard are expected to rely on multiple antennas at both transmitter and receiver to increase throughput and link reliability. However, these improvements come at a significant increase in signal processing and hence hardware complexity compared to existing single-antenna systems. This paper presents, to the best of the authors' knowledge, the first 4 /spl times/ 4 MIMO-OFDM WLAN physical layer ASIC based on the OFDM specifications of the IEEE 802.1 la standard. The ASIC achieves an uncoded throughput of 192 Mbps in a 20 MHz channel resulting in a spectral efficiency of 9.6 bits/s/Hz. We describe the hardware architectural differences to single-antenna OFDM systems as well as the extensions made necessary by the use of multiple antennas. Our implementation provides reference for the silicon complexity of MIMO-OFDM systems.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128005177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Physical random number generators for cryptographic application in mobile devices 移动设备中加密应用的物理随机数生成器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541644
S. Yasuda, T. Tanamoto, R. Ohba, K. Abe, H. Nozaki, S. Fujita
{"title":"Physical random number generators for cryptographic application in mobile devices","authors":"S. Yasuda, T. Tanamoto, R. Ohba, K. Abe, H. Nozaki, S. Fujita","doi":"10.1109/ESSCIR.2005.1541644","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541644","url":null,"abstract":"We present small random number generators using silicon devices that generate large fluctuating signal as noise source devices. Since the noise signal of these devices is very large, the noise signal can be directly input to an RC oscillator or a differential amplifier without preamplifiers. In this paper, we present a small physical random number generator using an astable multivibrator and post-processing circuits, which can generate excellent quality random numbers suitable for cryptographic applications. We also introduce the concept of random number generator using a filter circuit and a differential amplification for high bit rate application.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121491152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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