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Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.最新文献

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Autonomous di/dt noise control scheme for margin aware operation 基于余量感知的自主di/dt噪声控制方案
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541661
T. Nakura, M. Ikeda, K. Asada
{"title":"Autonomous di/dt noise control scheme for margin aware operation","authors":"T. Nakura, M. Ikeda, K. Asada","doi":"10.1109/ESSCIR.2005.1541661","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541661","url":null,"abstract":"This paper demonstrates the first trial of an autonomous and margin aware di/dt noise control scheme. A di/dt on the power line is detected by a mutual inductor, the induced voltage is multiplied by Gilbert multiplier and the following low pass filter outputs a DC voltage in proportion to the di/dt noise. The DC voltage is compared with reference voltages, and the modes of the internal circuit is controlled depending on the comparators output. By using this scheme, the di/dt noise power can be autonomously controlled to fall within a defined range set by the reference voltages. We use two operation modes here: all-active and half-active modes. Our experimental results show that the internal circuit oscillates between the all-active and the half-active modes, also show that the all/half ratio and the oscillation frequency changes depending on the reference voltages. It proves that our autonomous di/dt noise control scheme works as being designed.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127599422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 43dB ACR low-pass filter with automatic tuning for low-IF conversion DAB/T-DMB tuner IC 43dB ACR低通滤波器，自动调谐，用于低中频转换DAB/T-DMB调谐器IC
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541624
Seyeob Kim, Bonkee Kim, M. Jeong, Jung-Hwan Lee, Youngho Cho, Tae Wook Kim, Boeun Kim
{"title":"A 43dB ACR low-pass filter with automatic tuning for low-IF conversion DAB/T-DMB tuner IC","authors":"Seyeob Kim, Bonkee Kim, M. Jeong, Jung-Hwan Lee, Youngho Cho, Tae Wook Kim, Boeun Kim","doi":"10.1109/ESSCIR.2005.1541624","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541624","url":null,"abstract":"This paper provides a channel select low-pass filter with automatic cut-off frequency tuning circuit for low-IF conversion digital audio broadcasting (DAB) and terrestrial-digital multimedia broadcasting (T-DMB) tuner IC. This filter has 1.58MHz cut-off frequency, 20dB and 65dB stop band attenuation at 1.9MHz and 2.4MHz, respectively. The in-band IIP3 is -8.4dBV and 1dB desensitization is satisfied for 490mVpp interferer at 1.7MHz frequency offset. By using simple automatic tuning technique, less than +/-1.5% cut-off frequency error and more than 40dB adjacent channel rejection (ACR) are obtained. The low-pass filter is fabricated in 0.18/spl mu/m CMOS technology and consumes about 4.5mA with 1.8V power supply.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127784701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
An integrated optical receiver with wide-range timing discrimination characteristics 具有宽范围时辨特性的集成光接收机
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541653
S. Kurtti, J. Kostamovaara
{"title":"An integrated optical receiver with wide-range timing discrimination characteristics","authors":"S. Kurtti, J. Kostamovaara","doi":"10.1109/ESSCIR.2005.1541653","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541653","url":null,"abstract":"An integrated receiver channel with a wide dynamic range for a pulsed time-of-flight laser rangefinder was designed and tested. The timing discriminator is realized so that the received unipolar pulse is converted to a bipolar signal at the front-end of the receiver channel, thus gain control and off-chip components are not needed. The walk error is 110 ps, or 16 mm in distance, over the dynamic range 1:1600. The minimum detectable signal is 1.52 /spl mu/A with the required SNR of 10. The circuit was implemented in a 0.35-/spl mu/m SiGe BiCMOS process.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127895018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An on-chip self-calibration method for current mismatch in D/A converters D/A变换器电流失配的片上自校正方法
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541586
G. Radulov, P. Quinn, H. Hegt, A. Roermund
{"title":"An on-chip self-calibration method for current mismatch in D/A converters","authors":"G. Radulov, P. Quinn, H. Hegt, A. Roermund","doi":"10.1109/ESSCIR.2005.1541586","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541586","url":null,"abstract":"This paper presents an on-chip low-power self-calibration apparatus implemented in a 12-bit current-steering 250nm CMOS DAC. The DAC core consists of a noncalibrated binary LSB part and a calibrated thermometer MSB part. The thermometer currents are generated by combining a coarse 10-bit accurate current with a fine calibrating current provided by a small calibrating DAC (CALDAC). The magnitude of the fine current is determined in the digital domain and optimized for overall post-calibration accuracy. This digital process acquires mismatch error information from on an on-chip single bit ADC. The whole calibration process is executed once at chip power-up and the calibration results are recorded. During the normal operation of the DAC, no active calibration operations are present and the fine currents are kept static, so that the advantages of calibration are maintained even at very high conversion rates. The self-calibrated DAC achieves 12-bit static and dynamic linearity, while occupying smaller silicon area due to the intrinsic 10-bit accuracy of the DAC core.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124123781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
CMOS microelectrode array for bidirectional interaction with neuronal networks 用于与神经网络双向交互的CMOS微电极阵列
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541628
F. Heer, S. Hafizovic, W. Franks, T. Ugniwenko, A. Blau, C. Ziegler, A. Hierlemann
{"title":"CMOS microelectrode array for bidirectional interaction with neuronal networks","authors":"F. Heer, S. Hafizovic, W. Franks, T. Ugniwenko, A. Blau, C. Ziegler, A. Hierlemann","doi":"10.1109/ESSCIR.2005.1541628","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541628","url":null,"abstract":"We report on a microelectrode array for bidirectional communication (stimulation and recording) with electrogenic cells, for e.g., observing neuronal information processing in vitro. The chip overcomes the interconnect challenge that limits today's bidirectional microelectrode arrays. The array has been fabricated in industrial CMOS-technology with post-CMOS processing and comprises all necessary control circuitry and on-chip A/D-conversion. Measurements from neural cell cultures with amplitudes of 500 /spl mu/V are presented.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121788058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A novel UWB impulse-radio transmitter with all-digitally-controlled pulse generator 一种新型的带全数字控制脉冲发生器的超宽带脉冲无线电发射机
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541611
T. Norimatsu, R. Fujiwara, M. Kokubo, M. Miyazaki, Yasuyuki Okuma, Miki Hayakawa, Shinsuke Kobayashi, N. Koshizuka, Ken Sakamura
{"title":"A novel UWB impulse-radio transmitter with all-digitally-controlled pulse generator","authors":"T. Norimatsu, R. Fujiwara, M. Kokubo, M. Miyazaki, Yasuyuki Okuma, Miki Hayakawa, Shinsuke Kobayashi, N. Koshizuka, Ken Sakamura","doi":"10.1109/ESSCIR.2005.1541611","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541611","url":null,"abstract":"A novel transmitter for ultra-wideband (UWB) impulse radio was developed. The proposed architecture realizes low power, low complexity, and generation of a highly accurate pulse. The phase and amplitude of a pulse are controlled separately and digitally to generate a highly accurate pulse. This control method also contributes to the transmitter's low power and eliminates the need for a filter. The transmitter was fabricated by a 0.18-/spl mu/m bulk CMOS process. The core chip size is only 0.40 mm/sup 2/. Measurement of this transmitter found that the FCC spectrum mask is satisfied and average power dissipation is 29.7 mW under a supply voltage of 2.2 V. These results show that the developed UWB transmitter can generate an accurate pulse with low power and low complexity.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116523643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20MHz signal bandwidth 具有20MHz信号带宽的时间交错连续时间/spl δ //spl σ /调制器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541656
T. Caldwell, D. Johns
{"title":"A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20MHz signal bandwidth","authors":"T. Caldwell, D. Johns","doi":"10.1109/ESSCIR.2005.1541656","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541656","url":null,"abstract":"This paper presents the first implementation results for a time-interleaved continuous-time /spl Delta//spl Sigma/ modulator. The 3rd-order low-pass modulator operates at an oversampling ratio of 5 with a time-interleaving factor of 2 at sampling frequencies of 100MHz and 200MHz. It achieves an SNDR of 57dB and 49dB in signal bandwidths of 10MHz and 20MHz, respectively.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122331922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A new integrated charge pump architecture using dynamic biasing of pass transistors 一种利用通型晶体管动态偏置的集成电荷泵结构
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541564
L. Mensi, L. Colalongo, A. Richelli, Z. Kovács-Vajna
{"title":"A new integrated charge pump architecture using dynamic biasing of pass transistors","authors":"L. Mensi, L. Colalongo, A. Richelli, Z. Kovács-Vajna","doi":"10.1109/ESSCIR.2005.1541564","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541564","url":null,"abstract":"In this paper, a new charge pump architecture is presented: it is based on PMOS pass transistors with dynamic biasing of gates and bodies. By controlling the gate and body voltages of each pass transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. Furthermore, the overdrive voltage of the pass transistors grows progressively from the first to the last boost stage. This new architecture was developed and validated through simulations and experimental measurements on AMS 0.8/spl mu/m standard CMOS technology.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"51 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131072436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS 90nm CMOS的9-b 400 Msample/s流水线模数转换器
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541678
Charles T. Peach, A. Ravi, R. Bishop, K. Soumyanath, D. Allstot
{"title":"A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS","authors":"Charles T. Peach, A. Ravi, R. Bishop, K. Soumyanath, D. Allstot","doi":"10.1109/ESSCIR.2005.1541678","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541678","url":null,"abstract":"A 9-bit 400MS/s pipelined analog-to-digital converter (ADC) targeted for emerging wireless LAN applications is presented. The converter can be clocked up to 500 mega-samples per second (MSPS) with an input bandwidth of 100 MHz, while drawing 93mA from 1.5V. The ADC achieves 8.6 effective number of bits (ENOBs) at 10MHz input and 7.9 ENOBs at 80MHz input, without accounting for calibration or oversampling based enhancements. The architecture is a double-sampled switched-capacitor pipeline that converts on both phases of the sampling clock for improved power efficiency. A skew-insensitive sample-and-hold stage attenuates distortion caused by imperfectly phased sampling clocks.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132701128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Digital communication systems: the problem of analog interface circuits 数字通信系统:模拟接口电路的问题
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. Pub Date : 2005-12-05 DOI: 10.1109/ESSCIR.2005.1541650
M. Steyaert, F. Gobert, C. Hermans, P. Reynaert, B. Serneels
{"title":"Digital communication systems: the problem of analog interface circuits","authors":"M. Steyaert, F. Gobert, C. Hermans, P. Reynaert, B. Serneels","doi":"10.1109/ESSCIR.2005.1541650","DOIUrl":"https://doi.org/10.1109/ESSCIR.2005.1541650","url":null,"abstract":"Due to the use of deep sub-micron and nano technologies, the signal processing in the digital area becomes so powerful that the limitations are again situated in the analog front-end circuits. This becomes a huge problem in signal output drivers. The development of xDSL and RF systems all lack efficient power amplifiers, especially if they have to be realized in standard CMOS technologies. Another challenge is the design of wide-band receiver front-ends including low-noise input-matched CMOS amplifiers. An overview of the limitations, trends and some recent achievements from the open literature were analyzed and discussed.","PeriodicalId":239980,"journal":{"name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130854727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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